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/third_party/skia/src/core/
H A DSkRuntimeEffect.cpp607 skvm::Ptr uniPtr = skslUniforms.base; in Make()
908 // We were unable to build a cached (per-effect) program. Use the base-class fallback,
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DWasmTranslator.cpp1634 Body.base = Buffer.data(); in translate()
/third_party/protobuf/java/util/src/main/java/com/google/protobuf/util/
H A DJsonFormat.java33 import com.google.common.base.Preconditions;
/third_party/python/Lib/test/test_import/
H A D__init__.py348 base, ext = os.path.splitext(mod.__file__)
/third_party/python/Modules/cjkcodecs/
H A Dmappings_cn.h4054 DBCHAR base; member
/kernel/linux/linux-5.10/drivers/scsi/lpfc/
H A Dlpfc_sli.c5994 * Based on the resource size and count, correct the base and max in lpfc_sli4_alloc_extent()
6616 uint16_t count, base; in lpfc_sli4_alloc_resource_identifiers() local
6715 base = phba->sli4_hba.max_cfg_param.rpi_base; in lpfc_sli4_alloc_resource_identifiers()
6732 phba->sli4_hba.rpi_ids[i] = base + i; in lpfc_sli4_alloc_resource_identifiers()
6743 base = phba->sli4_hba.max_cfg_param.vpi_base; in lpfc_sli4_alloc_resource_identifiers()
6759 phba->vpi_ids[i] = base + i; in lpfc_sli4_alloc_resource_identifiers()
6770 base = phba->sli4_hba.max_cfg_param.xri_base; in lpfc_sli4_alloc_resource_identifiers()
6788 phba->sli4_hba.xri_ids[i] = base + i; in lpfc_sli4_alloc_resource_identifiers()
6799 base = phba->sli4_hba.max_cfg_param.vfi_base; in lpfc_sli4_alloc_resource_identifiers()
6816 phba->sli4_hba.vfi_ids[i] = base in lpfc_sli4_alloc_resource_identifiers()
[all...]
/kernel/linux/linux-6.6/drivers/scsi/lpfc/
H A Dlpfc_sli.c6474 * Based on the resource size and count, correct the base and max in lpfc_sli4_alloc_extent()
7145 uint16_t count, base; in lpfc_sli4_alloc_resource_identifiers() local
7244 base = phba->sli4_hba.max_cfg_param.rpi_base; in lpfc_sli4_alloc_resource_identifiers()
7261 phba->sli4_hba.rpi_ids[i] = base + i; in lpfc_sli4_alloc_resource_identifiers()
7272 base = phba->sli4_hba.max_cfg_param.vpi_base; in lpfc_sli4_alloc_resource_identifiers()
7288 phba->vpi_ids[i] = base + i; in lpfc_sli4_alloc_resource_identifiers()
7299 base = phba->sli4_hba.max_cfg_param.xri_base; in lpfc_sli4_alloc_resource_identifiers()
7317 phba->sli4_hba.xri_ids[i] = base + i; in lpfc_sli4_alloc_resource_identifiers()
7328 base = phba->sli4_hba.max_cfg_param.vfi_base; in lpfc_sli4_alloc_resource_identifiers()
7345 phba->sli4_hba.vfi_ids[i] = base in lpfc_sli4_alloc_resource_identifiers()
[all...]
/kernel/linux/linux-5.10/arch/m68k/ifpsp060/src/
H A Dpfpsp.S4935 # " " " w/ " (base displacement): (bd, An, Xn) #
4941 bsr.l fetch_dreg # fetch base areg
5034 # " " w/ " (base displacement): (bd, PC, An) #
5046 mov.l EXC_EXTWPTR(%a6),%a0 # put base in a0
5047 subq.l &0x2,%a0 # adjust base
5082 # d3 = base
5092 mov.l %a0,%d3 # put base in d3
5116 # base address (passed as parameter in d3):
5123 # base displacement:
5152 add.l %d0,%d3 # base
[all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/e1000e/
H A Dich8lan.c87 u32 base:13; /* 0:12 Protected Range Base */ member
615 /* Set the base address for flash register access */ in e1000_init_nvm_params_ich8lan()
1864 * in by addr. For 82579, RAR[0] is the base address register that is to
1967 * in by addr. For LPT, RAR[0] is the base address register that is to
4176 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; in e1000e_write_protect_nvm_ich8lan()
4507 /* Start with the base address, then add the sector offset. */ in e1000_erase_flash_bank_ich8lan()
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/i40e/
H A Di40e_virtchnl_pf.c602 tx_ctx.base = info->dma_ring_addr / 128; in i40e_config_vsi_tx_queue()
667 rx_ctx.base = info->dma_ring_addr / 128; in i40e_config_vsi_rx_queue()
2650 * Returns the base item index of the queue, or negative for error
/kernel/linux/linux-6.6/arch/m68k/ifpsp060/src/
H A Dpfpsp.S4935 # " " " w/ " (base displacement): (bd, An, Xn) #
4941 bsr.l fetch_dreg # fetch base areg
5034 # " " w/ " (base displacement): (bd, PC, An) #
5046 mov.l EXC_EXTWPTR(%a6),%a0 # put base in a0
5047 subq.l &0x2,%a0 # adjust base
5082 # d3 = base
5092 mov.l %a0,%d3 # put base in d3
5116 # base address (passed as parameter in d3):
5123 # base displacement:
5152 add.l %d0,%d3 # base
[all...]
/kernel/linux/linux-5.10/drivers/misc/habanalabs/goya/
H A Dgoya_security.c15 * @block: block base address
18 static void goya_pb_set_block(struct hl_device *hdev, u64 base) in goya_pb_set_block() argument
20 u32 pb_addr = base - CFG_BASE + PROT_BITS_OFFS; in goya_pb_set_block()
/kernel/linux/linux-5.10/drivers/net/ethernet/netronome/nfp/bpf/
H A Djit.c256 static void emit_rtn(struct nfp_prog *nfp_prog, swreg base, u8 defer) in emit_rtn() argument
261 err = swreg_to_unrestricted(reg_none(), base, reg_imm(0), &reg); in emit_rtn()
4074 * - Their address base registers are the same.
4148 * base register. in cross_mem_access()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_display_power.c1431 intel_crt_reset(&encoder->base); in vlv_display_power_well_init()
1818 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_powergate_lanes()
/kernel/linux/linux-6.6/drivers/net/ethernet/netronome/nfp/bpf/
H A Djit.c256 static void emit_rtn(struct nfp_prog *nfp_prog, swreg base, u8 defer) in emit_rtn() argument
261 err = swreg_to_unrestricted(reg_none(), base, reg_imm(0), &reg); in emit_rtn()
4080 * - Their address base registers are the same.
4154 * base register. in cross_mem_access()
/kernel/linux/linux-6.6/drivers/net/ethernet/intel/e1000e/
H A Dich8lan.c87 u32 base:13; /* 0:12 Protected Range Base */ member
621 /* Set the base address for flash register access */ in e1000_init_nvm_params_ich8lan()
1878 * in by addr. For 82579, RAR[0] is the base address register that is to
1981 * in by addr. For LPT, RAR[0] is the base address register that is to
4192 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; in e1000e_write_protect_nvm_ich8lan()
4523 /* Start with the base address, then add the sector offset. */ in e1000_erase_flash_bank_ich8lan()
/kernel/linux/linux-6.6/drivers/net/ethernet/intel/i40e/
H A Di40e_virtchnl_pf.c657 tx_ctx.base = info->dma_ring_addr / 128; in i40e_config_vsi_tx_queue()
722 rx_ctx.base = info->dma_ring_addr / 128; in i40e_config_vsi_rx_queue()
2710 * Returns the base item index of the queue, or negative for error
/kernel/linux/linux-6.6/fs/nfsd/
H A Dnfs4xdr.c4116 unsigned int base = xdr->buf->page_len & ~PAGE_MASK; in nfsd4_encode_readv() local
4125 read->rd_offset, &maxcount, base, in nfsd4_encode_readv()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_device.c3632 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base); in amdgpu_device_init()
4736 drm_sched_increase_karma(&job->base); in amdgpu_device_pre_asic_reset()
4916 /* Since the mode1 reset affects base ip blocks, the in amdgpu_do_asic_reset()
5264 drm_sched_stop(&ring->sched, job ? &job->base : NULL); in amdgpu_device_gpu_recover()
5279 * job->base holds a reference to parent fence in amdgpu_device_gpu_recover()
/kernel/linux/linux-6.6/drivers/accel/habanalabs/goya/
H A Dgoya_security.c15 * @block: block base address
18 static void goya_pb_set_block(struct hl_device *hdev, u64 base) in goya_pb_set_block() argument
20 u32 pb_addr = base - CFG_BASE + PROT_BITS_OFFS; in goya_pb_set_block()
/third_party/node/deps/v8/src/compiler/backend/arm64/
H A Dcode-generator-arm64.cc1008 Register base = offset.from_stack_pointer() ? sp : fp; in AssembleArchInstruction() local
1009 __ Add(i.OutputRegister(0), base, Operand(offset.offset())); in AssembleArchInstruction()
/third_party/node/deps/v8/src/builtins/arm/
H A Dbuiltins-arm.cc577 __ vmov(kDoubleRegZero, base::Double(0.0)); in Generate_JSEntryVariant()
2779 DCHECK(base::bits::IsPowerOfTwo(frame_alignment)); in Generate_CEntry()
/third_party/node/deps/v8/src/codegen/x64/
H A Dassembler-x64.cc18 #include "src/base/bits.h"
19 #include "src/base/cpu.h"
20 #include "src/base/platform/wrappers.h"
91 base::CPU cpu; in ProbeImpl()
178 // Mode 0 with rbp/r13 as ModR/M or SIB base register always has a 32-bit in Operand()
180 bool is_baseless = (mode == 0) && (base_reg == 0x05); // No base or RIP base. in Operand()
183 // Mode 2 or mode 0 with rbp/r13 as base: Word displacement. in Operand()
220 // Start with only low three bits of base register. Initial decoding in AddressUsesRegister()
229 // Add REX.B to get the full base registe in AddressUsesRegister()
[all...]
/third_party/node/deps/v8/src/wasm/baseline/mips64/
H A Dliftoff-assembler-mips64.h8 #include "src/base/platform/wrappers.h"
125 inline void Store(LiftoffAssembler* assm, Register base, int32_t offset, in Store() argument
127 MemOperand dst(base, offset); in Store()
/third_party/libabigail/src/
H A Dabg-reader.cc3173 /// element representing either a function symbols data base, or a
3181 /// data base, false if we should look for a variable symbols data
3182 /// base.
4801 if (xmlStrEqual(n->name, BAD_CAST("base-class"))) in build_class_decl()
4819 // the class we have already has this base class, so we in build_class_decl()
4829 shared_ptr<class_decl::base_spec> base (new class_decl::base_spec in build_class_decl()
4835 decl->add_base_specifier(base); in build_class_decl()

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