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/kernel/linux/linux-6.6/drivers/irqchip/
H A Dirq-ftintc010.c43 * @base: memory offset in virtual memory
48 void __iomem *base; member
58 mask = readl(FT010_IRQ_MASK(f->base)); in ft010_irq_mask()
60 writel(mask, FT010_IRQ_MASK(f->base)); in ft010_irq_mask()
68 mask = readl(FT010_IRQ_MASK(f->base)); in ft010_irq_unmask()
70 writel(mask, FT010_IRQ_MASK(f->base)); in ft010_irq_unmask()
77 writel(BIT(irqd_to_hwirq(d)), FT010_IRQ_CLEAR(f->base)); in ft010_irq_ack()
86 mode = readl(FT010_IRQ_MODE(f->base)); in ft010_irq_set_type()
87 polarity = readl(FT010_IRQ_POLARITY(f->base)); in ft010_irq_set_type()
111 writel(mode, FT010_IRQ_MODE(f->base)); in ft010_irq_set_type()
[all...]
/kernel/linux/linux-6.6/drivers/mailbox/
H A Darmada-37xx-rwtm-mailbox.c39 void __iomem *base; member
49 rx_msg.retval = readl(mbox->base + RWTM_MBOX_RETURN_STATUS); in a37xx_mbox_receive()
51 rx_msg.status[i] = readl(mbox->base + RWTM_MBOX_STATUS(i)); in a37xx_mbox_receive()
62 reg = readl(mbox->base + RWTM_HOST_INT_RESET); in a37xx_mbox_irq_handler()
70 writel(reg, mbox->base + RWTM_HOST_INT_RESET); in a37xx_mbox_irq_handler()
87 reg = readl(mbox->base + RWTM_MBOX_FIFO_STATUS); in a37xx_mbox_send_data()
97 writel(msg->args[i], mbox->base + RWTM_MBOX_PARAM(i)); in a37xx_mbox_send_data()
98 writel(msg->command, mbox->base + RWTM_MBOX_COMMAND); in a37xx_mbox_send_data()
117 reg = readl(mbox->base + RWTM_HOST_INT_MASK); in a37xx_mbox_startup()
119 writel(reg, mbox->base in a37xx_mbox_startup()
[all...]
/third_party/mesa3d/src/virtio/vulkan/
H A Dvn_common.h155 /* base class of vn_instance */
157 struct vk_instance base; member
161 /* base class of vn_physical_device */
163 struct vk_physical_device base; member
167 /* base class of vn_device */
169 struct vk_device base; member
173 /* base class of other driver objects */
175 struct vk_object_base base; member
272 VkResult result = vk_instance_init(&instance->base, supported_extensions, in vn_instance_base_init()
281 vk_instance_finish(&instance->base); in vn_instance_base_fini()
[all...]
/third_party/icu/icu4c/source/test/intltest/
H A Dpunyref.cpp51 enum { base = 36, tmin = 1, tmax = 26, skew = 38, damp = 700, enumerator
63 /* base-1, or base if cp is does not represent a value. */
68 cp - 97 < 26 ? cp - 97 : static_cast<punycode_uint>(base); in decode_digit()
73 /* the range 0 to base-1. The lowercase form is used unless flag is */
119 for (k = 0; delta > ((base - tmin) * tmax) / 2; k += base) { in adapt()
120 delta /= base - tmin; in adapt()
123 return k + (base - tmin + 1) * delta / (delta + skew); in adapt()
192 for (q = delta, k = base; ; in punycode_encode()
[all...]
/third_party/node/deps/v8/src/libplatform/
H A Ddefault-foreground-task-runner.cc7 #include "src/base/platform/mutex.h"
30 base::MutexGuard guard(&lock_); in Terminate()
41 const base::MutexGuard&) { in PostTaskLocked()
48 base::MutexGuard guard(&lock_); in PostTask()
58 Nestability nestability, const base::MutexGuard&) { in PostDelayedTaskLocked()
68 base::MutexGuard guard(&lock_); in PostDelayedTask()
74 base::MutexGuard guard(&lock_); in PostNonNestableDelayedTask()
80 base::MutexGuard guard(&lock_); in PostIdleTask()
91 base::MutexGuard guard(&lock_); in PostNonNestableTask()
108 const base in MoveExpiredDelayedTasks()
39 PostTaskLocked(std::unique_ptr<Task> task, Nestability nestability, const base::MutexGuard&) PostTaskLocked() argument
56 PostDelayedTaskLocked( std::unique_ptr<Task> task, double delay_in_seconds, Nestability nestability, const base::MutexGuard&) PostDelayedTaskLocked() argument
143 PopTaskFromDelayedQueueLocked( const base::MutexGuard&, Nestability* nestability) PopTaskFromDelayedQueueLocked() argument
172 WaitForTaskLocked(const base::MutexGuard&) WaitForTaskLocked() argument
[all...]
/third_party/node/deps/v8/src/profiler/
H A Dstrings-storage.cc9 #include "src/base/strings.h"
24 for (base::HashMap::Entry* p = names_.Start(); p != nullptr; in ~StringsStorage()
31 base::MutexGuard guard(&mutex_); in GetCopy()
33 base::HashMap::Entry* entry = GetEntry(src, len); in GetCopy()
35 base::Vector<char> dst = base::Vector<char>::New(len + 1); in GetCopy()
36 base::StrNCpy(dst, src, len); in GetCopy()
55 base::MutexGuard guard(&mutex_); in AddOrDisposeString()
56 base::HashMap::Entry* entry = GetEntry(str, len); in AddOrDisposeString()
70 base in GetVFormatted()
[all...]
/third_party/mesa3d/src/gallium/auxiliary/pipebuffer/
H A Dpb_bufmgr_cache.c53 struct pb_buffer base; member
62 struct pb_manager base; member
101 assert(!pipe_is_referenced(&buf->base.reference)); in _pb_cache_buffer_destroy()
214 return &buf->base; in pb_cache_manager_create_buffer()
238 pipe_reference_init(&buf->base.reference, 1); in pb_cache_manager_create_buffer()
239 buf->base.alignment_log2 = buf->buffer->alignment_log2; in pb_cache_manager_create_buffer()
240 buf->base.usage = buf->buffer->usage; in pb_cache_manager_create_buffer()
241 buf->base.size = buf->buffer->size; in pb_cache_manager_create_buffer()
243 buf->base.vtbl = &pb_cache_buffer_vtbl; in pb_cache_manager_create_buffer()
245 pb_cache_init_entry(&mgr->cache, &buf->cache_entry, &buf->base, in pb_cache_manager_create_buffer()
[all...]
/kernel/linux/linux-5.10/drivers/crypto/inside-secure/
H A Dsafexcel_ring.c23 cdr->base = dmam_alloc_coherent(priv->dev, in safexcel_init_ring_descriptors()
26 if (!cdr->base) in safexcel_init_ring_descriptors()
28 cdr->write = cdr->base; in safexcel_init_ring_descriptors()
29 cdr->base_end = cdr->base + cdr->offset * (EIP197_DEFAULT_RING_SIZE - 1); in safexcel_init_ring_descriptors()
30 cdr->read = cdr->base; in safexcel_init_ring_descriptors()
48 cdesc = cdr->base; in safexcel_init_ring_descriptors()
60 rdr->base = dmam_alloc_coherent(priv->dev, in safexcel_init_ring_descriptors()
63 if (!rdr->base) in safexcel_init_ring_descriptors()
65 rdr->write = rdr->base; in safexcel_init_ring_descriptors()
66 rdr->base_end = rdr->base in safexcel_init_ring_descriptors()
[all...]
/kernel/linux/linux-5.10/drivers/input/touchscreen/
H A Dsun4i-ts.c109 void __iomem *base; member
122 x = readl(ts->base + TP_DATA); in sun4i_ts_irq_handle_input()
123 y = readl(ts->base + TP_DATA); in sun4i_ts_irq_handle_input()
152 reg_val = readl(ts->base + TP_INT_FIFOS); in sun4i_ts_irq()
155 ts->temp_data = readl(ts->base + TEMP_DATA); in sun4i_ts_irq()
160 writel(reg_val, ts->base + TP_INT_FIFOS); in sun4i_ts_irq()
171 TP_UP_IRQ_EN(1), ts->base + TP_INT_FIFOC); in sun4i_ts_open()
181 writel(TEMP_IRQ_EN(1), ts->base + TP_INT_FIFOC); in sun4i_ts_close()
304 ts->base = devm_platform_ioremap_resource(pdev, 0); in sun4i_ts_probe()
305 if (IS_ERR(ts->base)) in sun4i_ts_probe()
[all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/qualcomm/emac/
H A Demac-sgmii.c97 val = readl(phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2); in emac_sgmii_link_init()
100 writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2); in emac_sgmii_link_init()
108 writel_relaxed(irq_bits, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR); in emac_sgmii_irq_clear()
109 writel_relaxed(IRQ_GLOBAL_CLEAR, phy->base + EMAC_SGMII_PHY_IRQ_CMD); in emac_sgmii_irq_clear()
117 if (readl_poll_timeout_atomic(phy->base + in emac_sgmii_irq_clear()
127 writel_relaxed(0, phy->base + EMAC_SGMII_PHY_IRQ_CMD); in emac_sgmii_irq_clear()
128 writel_relaxed(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR); in emac_sgmii_irq_clear()
145 status = readl(phy->base + EMAC_SGMII_PHY_INTERRUPT_STATUS); in emac_sgmii_interrupt()
185 val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2); in emac_sgmii_reset_prepare()
186 writel(((val & ~PHY_RESET) | PHY_RESET), phy->base in emac_sgmii_reset_prepare()
[all...]
/kernel/linux/linux-5.10/drivers/pci/controller/
H A Dpcie-tango.c21 void __iomem *base; member
29 unsigned long status, base, virq, idx, pos = 0; in tango_msi_isr() local
35 base = round_down(pos, 32); in tango_msi_isr()
36 status = readl_relaxed(pcie->base + SMP8759_STATUS + base / 8); in tango_msi_isr()
38 virq = irq_find_mapping(pcie->dom, base + idx); in tango_msi_isr()
41 pos = base + 32; in tango_msi_isr()
54 writel_relaxed(bit, pcie->base + SMP8759_STATUS + offset); in tango_ack()
66 val = readl_relaxed(pcie->base + SMP8759_ENABLE + offset); in update_msi_enable()
68 writel_relaxed(val, pcie->base in update_msi_enable()
[all...]
/kernel/linux/linux-5.10/sound/soc/xilinx/
H A Dxlnx_spdif.c50 void __iomem *base; member
60 val = readl(ctx->base + XSPDIF_IRQ_STS_REG); in xlnx_spdifrx_irq_handler()
63 ctx->base + XSPDIF_IRQ_STS_REG); in xlnx_spdifrx_irq_handler()
64 val = readl(ctx->base + in xlnx_spdifrx_irq_handler()
67 ctx->base + XSPDIF_IRQ_ENABLE_REG); in xlnx_spdifrx_irq_handler()
83 val = readl(ctx->base + XSPDIF_CONTROL_REG); in xlnx_spdif_startup()
85 writel(val, ctx->base + XSPDIF_CONTROL_REG); in xlnx_spdif_startup()
89 ctx->base + XSPDIF_IRQ_ENABLE_REG); in xlnx_spdif_startup()
91 ctx->base + XSPDIF_GLOBAL_IRQ_ENABLE_REG); in xlnx_spdif_startup()
102 writel(XSPDIF_SOFT_RESET_VALUE, ctx->base in xlnx_spdif_shutdown()
[all...]
/kernel/linux/linux-5.10/drivers/perf/hisilicon/
H A Dhisi_uncore_ddrc_pmu.c75 return readl(ddrc_pmu->base + hisi_ddrc_pmu_get_counter_offset(idx)); in hisi_ddrc_pmu_read_counter()
89 ddrc_pmu->base + hisi_ddrc_pmu_get_counter_offset(idx)); in hisi_ddrc_pmu_write_counter()
106 val = readl(ddrc_pmu->base + DDRC_PERF_CTRL); in hisi_ddrc_pmu_start_counters()
108 writel(val, ddrc_pmu->base + DDRC_PERF_CTRL); in hisi_ddrc_pmu_start_counters()
116 val = readl(ddrc_pmu->base + DDRC_PERF_CTRL); in hisi_ddrc_pmu_stop_counters()
118 writel(val, ddrc_pmu->base + DDRC_PERF_CTRL); in hisi_ddrc_pmu_stop_counters()
127 val = readl(ddrc_pmu->base + DDRC_EVENT_CTRL); in hisi_ddrc_pmu_enable_counter()
129 writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL); in hisi_ddrc_pmu_enable_counter()
138 val = readl(ddrc_pmu->base + DDRC_EVENT_CTRL); in hisi_ddrc_pmu_disable_counter()
140 writel(val, ddrc_pmu->base in hisi_ddrc_pmu_disable_counter()
[all...]
/kernel/linux/linux-5.10/drivers/reset/
H A Dreset-npcm.c59 void __iomem *base; member
71 writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR); in npcm_rc_restart()
89 stat = readl(rc->base + ctrl_offset); in npcm_rc_setclear_reset()
91 writel(stat | rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset()
93 writel(stat & ~rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset()
117 return (readl(rc->base + ctrl_offset) & rst_bit); in npcm_rc_status()
188 iprst1 = readl(rc->base + NPCM_IPSRST1); in npcm_usb_reset()
189 iprst2 = readl(rc->base + NPCM_IPSRST2); in npcm_usb_reset()
190 iprst3 = readl(rc->base + NPCM_IPSRST3); in npcm_usb_reset()
197 writel(iprst1, rc->base in npcm_usb_reset()
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/qualcomm/emac/
H A Demac-sgmii.c99 val = readl(phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2); in emac_sgmii_link_init()
102 writel(val, phy->base + EMAC_SGMII_PHY_AUTONEG_CFG2); in emac_sgmii_link_init()
110 writel_relaxed(irq_bits, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR); in emac_sgmii_irq_clear()
111 writel_relaxed(IRQ_GLOBAL_CLEAR, phy->base + EMAC_SGMII_PHY_IRQ_CMD); in emac_sgmii_irq_clear()
119 if (readl_poll_timeout_atomic(phy->base + in emac_sgmii_irq_clear()
129 writel_relaxed(0, phy->base + EMAC_SGMII_PHY_IRQ_CMD); in emac_sgmii_irq_clear()
130 writel_relaxed(0, phy->base + EMAC_SGMII_PHY_INTERRUPT_CLEAR); in emac_sgmii_irq_clear()
147 status = readl(phy->base + EMAC_SGMII_PHY_INTERRUPT_STATUS); in emac_sgmii_interrupt()
187 val = readl(phy->base + EMAC_EMAC_WRAPPER_CSR2); in emac_sgmii_reset_prepare()
188 writel(((val & ~PHY_RESET) | PHY_RESET), phy->base in emac_sgmii_reset_prepare()
[all...]
/kernel/linux/linux-6.6/drivers/pwm/
H A Dpwm-bcm-kona.c60 void __iomem *base; member
75 unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_prepare_for_settings()
79 writel(value, kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_prepare_for_settings()
90 unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_apply_settings()
95 writel(value, kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_apply_settings()
143 value = readl(kp->base + PRESCALE_OFFSET); in kona_pwmc_config()
146 writel(value, kp->base + PRESCALE_OFFSET); in kona_pwmc_config()
148 writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan)); in kona_pwmc_config()
150 writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan)); in kona_pwmc_config()
173 value = readl(kp->base in kona_pwmc_set_polarity()
[all...]
H A Dpwm-hibvt.c38 void __iomem *base; member
71 static void hibvt_pwm_set_bits(void __iomem *base, u32 offset, in hibvt_pwm_set_bits() argument
74 void __iomem *address = base + offset; in hibvt_pwm_set_bits()
87 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_enable()
95 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_disable()
110 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm), in hibvt_pwm_config()
113 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm), in hibvt_pwm_config()
124 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_set_polarity()
127 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_set_polarity()
135 void __iomem *base; in hibvt_pwm_get_state() local
[all...]
H A Dpwm-microchip-core.c59 void __iomem *base; member
85 channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset); in mchp_core_pwm_enable()
89 writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset); in mchp_core_pwm_enable()
181 writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm)); in mchp_core_pwm_apply_duty()
182 writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm)); in mchp_core_pwm_apply_duty()
317 hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE); in mchp_core_pwm_apply_locked()
318 hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD); in mchp_core_pwm_apply_locked()
349 writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE); in mchp_core_pwm_apply_locked()
350 writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD); in mchp_core_pwm_apply_locked()
409 prescale = readb_relaxed(mchp_core_pwm->base in mchp_core_pwm_get_state()
[all...]
/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-apple-nco.c35 * The REG_DIV register indirectly expresses a base integer divisor, roughly
37 * base divisor is adjusted on a cycle-by-cycle basis based on the state of a
68 void __iomem *base; member
82 val = readl_relaxed(chan->base + REG_CTRL); in applnco_enable_nolock()
83 writel_relaxed(val | CTRL_ENABLE, chan->base + REG_CTRL); in applnco_enable_nolock()
91 val = readl_relaxed(chan->base + REG_CTRL); in applnco_disable_nolock()
92 writel_relaxed(val & ~CTRL_ENABLE, chan->base + REG_CTRL); in applnco_disable_nolock()
99 return (readl_relaxed(chan->base + REG_CTRL) & CTRL_ENABLE) != 0; in applnco_is_enabled()
175 writel_relaxed(div, chan->base + REG_DIV); in applnco_set_rate()
176 writel_relaxed(inc1, chan->base in applnco_set_rate()
261 void __iomem *base; applnco_probe() local
[all...]
/kernel/linux/linux-6.6/drivers/clocksource/
H A Dtimer-sun5i.c37 void __iomem *base; member
60 u32 old = readl(ce->base + TIMER_CNTVAL_LO_REG(1)); in sun5i_clkevt_sync()
62 while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) in sun5i_clkevt_sync()
68 u32 val = readl(ce->base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
69 writel(val & ~TIMER_CTL_ENABLE, ce->base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
76 writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer)); in sun5i_clkevt_time_setup()
81 u32 val = readl(ce->base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_start()
89 ce->base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_start()
135 writel(0x1, ce->base + TIMER_IRQ_ST_REG); in sun5i_timer_interrupt()
145 return ~readl(cs->base in sun5i_clksrc_read()
176 void __iomem *base = cs->base; sun5i_setup_clocksource() local
203 void __iomem *base = ce->base; sun5i_setup_clockevent() local
[all...]
/kernel/linux/linux-6.6/drivers/crypto/inside-secure/
H A Dsafexcel_ring.c23 cdr->base = dmam_alloc_coherent(priv->dev, in safexcel_init_ring_descriptors()
26 if (!cdr->base) in safexcel_init_ring_descriptors()
28 cdr->write = cdr->base; in safexcel_init_ring_descriptors()
29 cdr->base_end = cdr->base + cdr->offset * (EIP197_DEFAULT_RING_SIZE - 1); in safexcel_init_ring_descriptors()
30 cdr->read = cdr->base; in safexcel_init_ring_descriptors()
48 cdesc = cdr->base; in safexcel_init_ring_descriptors()
60 rdr->base = dmam_alloc_coherent(priv->dev, in safexcel_init_ring_descriptors()
63 if (!rdr->base) in safexcel_init_ring_descriptors()
65 rdr->write = rdr->base; in safexcel_init_ring_descriptors()
66 rdr->base_end = rdr->base in safexcel_init_ring_descriptors()
[all...]
/kernel/linux/linux-6.6/drivers/input/touchscreen/
H A Dsun4i-ts.c109 void __iomem *base; member
122 x = readl(ts->base + TP_DATA); in sun4i_ts_irq_handle_input()
123 y = readl(ts->base + TP_DATA); in sun4i_ts_irq_handle_input()
152 reg_val = readl(ts->base + TP_INT_FIFOS); in sun4i_ts_irq()
155 ts->temp_data = readl(ts->base + TEMP_DATA); in sun4i_ts_irq()
160 writel(reg_val, ts->base + TP_INT_FIFOS); in sun4i_ts_irq()
171 TP_UP_IRQ_EN(1), ts->base + TP_INT_FIFOC); in sun4i_ts_open()
181 writel(TEMP_IRQ_EN(1), ts->base + TP_INT_FIFOC); in sun4i_ts_close()
304 ts->base = devm_platform_ioremap_resource(pdev, 0); in sun4i_ts_probe()
305 if (IS_ERR(ts->base)) in sun4i_ts_probe()
[all...]
/kernel/linux/linux-6.6/sound/soc/xilinx/
H A Dxlnx_spdif.c50 void __iomem *base; member
60 val = readl(ctx->base + XSPDIF_IRQ_STS_REG); in xlnx_spdifrx_irq_handler()
63 ctx->base + XSPDIF_IRQ_STS_REG); in xlnx_spdifrx_irq_handler()
64 val = readl(ctx->base + in xlnx_spdifrx_irq_handler()
67 ctx->base + XSPDIF_IRQ_ENABLE_REG); in xlnx_spdifrx_irq_handler()
83 val = readl(ctx->base + XSPDIF_CONTROL_REG); in xlnx_spdif_startup()
85 writel(val, ctx->base + XSPDIF_CONTROL_REG); in xlnx_spdif_startup()
89 ctx->base + XSPDIF_IRQ_ENABLE_REG); in xlnx_spdif_startup()
91 ctx->base + XSPDIF_GLOBAL_IRQ_ENABLE_REG); in xlnx_spdif_startup()
102 writel(XSPDIF_SOFT_RESET_VALUE, ctx->base in xlnx_spdif_shutdown()
[all...]
/third_party/mesa3d/src/egl/drivers/dri2/
H A Dplatform_surfaceless.c46 dri2_surf->base.Width, in surfaceless_alloc_image()
47 dri2_surf->base.Height, in surfaceless_alloc_image()
57 dri2_egl_display(dri2_surf->base.Resource.Display); in surfaceless_free_images()
78 dri2_egl_display(dri2_surf->base.Resource.Display); in surfaceless_image_get_buffers()
130 if (!dri2_init_surface(&dri2_surf->base, disp, type, conf, attrib_list, in dri2_surfaceless_create_surface()
135 dri2_surf->base.GLColorspace); in dri2_surfaceless_create_surface()
149 return &dri2_surf->base; in dri2_surfaceless_create_surface()
204 .base = { __DRI_KOPPER_LOADER, 1 },
210 .base = { __DRI_IMAGE_LOADER, 2 },
217 &image_loader_extension.base,
[all...]
/third_party/node/deps/v8/src/libplatform/tracing/
H A Dtracing-controller.cc10 #include "src/base/atomicops.h"
11 #include "src/base/platform/mutex.h"
12 #include "src/base/platform/time.h"
13 #include "src/base/platform/wrappers.h"
22 #include "src/base/platform/platform.h"
23 #include "src/base/platform/semaphore.h"
70 v8::base::AtomicWord g_category_index = g_num_builtin_categories;
73 TracingController::TracingController() { mutex_.reset(new base::Mutex()); } in TracingController()
81 base::MutexGuard lock(mutex_.get()); in ~TracingController()
109 return base in CurrentTimestampMicroseconds()
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