Searched defs:adev (Results 1126 - 1150 of 1159) sorted by relevance

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/kernel/linux/linux-6.6/drivers/iommu/amd/
H A D	iommu.c	93 struct acpi_device *adev = ACPI_COMPANION(dev); in get_acpihid_device_id() local
/kernel/linux/linux-6.6/sound/soc/qcom/qdsp6/
H A D	q6afe.c	870 static int q6afe_callback(struct apr_device *adev, struct apr_resp_pkt *data) in q6afe_callback() argument 1731 static int q6afe_probe(struct apr_device *adev) in q6afe_probe() argument
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A D	gfx_v10_0.c	1367 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v) in gfx_v10_rlcg_wreg() argument 3236 struct amdgpu_device *adev = kiq_ring->adev; gfx10_kiq_map_queues() local 3333 gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) gfx_v10_0_set_kiq_pm4_funcs() argument 3338 gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) gfx_v10_0_init_spm_golden_registers() argument 3361 gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) gfx_v10_0_init_golden_registers() argument 3408 gfx_v10_0_scratch_init(struct amdgpu_device *adev) gfx_v10_0_scratch_init() argument 3450 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_test_ring() local 3497 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_test_ib() local 3549 gfx_v10_0_free_microcode(struct amdgpu_device *adev) gfx_v10_0_free_microcode() argument 3567 gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) gfx_v10_0_check_fw_write_wait() argument 3596 gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) gfx_v10_0_init_rlc_ext_microcode() argument 3617 gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev) gfx_v10_0_init_rlc_iram_dram_microcode() argument 3628 gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) gfx_v10_0_navi10_gfxoff_should_enable() argument 3645 gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) gfx_v10_0_check_gfxoff_flag() argument 3660 gfx_v10_0_init_microcode(struct amdgpu_device *adev) gfx_v10_0_init_microcode() argument 3946 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) gfx_v10_0_get_csb_size() argument 3976 gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer) gfx_v10_0_get_csb_buffer() argument 4024 gfx_v10_0_rlc_fini(struct amdgpu_device *adev) gfx_v10_0_rlc_fini() argument 4037 gfx_v10_0_rlc_init(struct amdgpu_device *adev) gfx_v10_0_rlc_init() argument 4060 gfx_v10_0_mec_fini(struct amdgpu_device *adev) gfx_v10_0_mec_fini() argument 4066 gfx_v10_0_me_init(struct amdgpu_device *adev) gfx_v10_0_me_init() argument 4081 gfx_v10_0_mec_init(struct amdgpu_device *adev) gfx_v10_0_mec_init() argument 4143 wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) wave_read_ind() argument 4151 wave_read_regs(struct amdgpu_device *adev, uint32_t wave, uint32_t thread, uint32_t regno, uint32_t num, uint32_t *out) wave_read_regs() argument 4164 gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) gfx_v10_0_read_wave_data() argument 4190 gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) gfx_v10_0_read_wave_sgprs() argument 4201 gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst) gfx_v10_0_read_wave_vgprs() argument 4211 gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, u32 me, u32 pipe, u32 q, u32 vm) gfx_v10_0_select_me_pipe_q() argument 4228 gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) gfx_v10_0_gpu_early_init() argument 4284 gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, int me, int pipe, int queue) gfx_v10_0_gfx_ring_init() argument 4315 gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, int mec, int pipe, int queue) gfx_v10_0_compute_ring_init() argument 4356 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_sw_init() local 4498 gfx_v10_0_pfp_fini(struct amdgpu_device *adev) gfx_v10_0_pfp_fini() argument 4505 gfx_v10_0_ce_fini(struct amdgpu_device *adev) gfx_v10_0_ce_fini() argument 4512 gfx_v10_0_me_fini(struct amdgpu_device *adev) gfx_v10_0_me_fini() argument 4522 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_sw_fini() local 4547 gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) gfx_v10_0_select_se_sh() argument 4574 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) gfx_v10_0_get_rb_active_bitmap() argument 4590 gfx_v10_0_setup_rb(struct amdgpu_device *adev) gfx_v10_0_setup_rb() argument 4619 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) gfx_v10_0_init_pa_sc_tile_steering_override() argument 4660 gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) gfx_v10_0_init_compute_vmid() argument 4693 gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) gfx_v10_0_init_gds_vmid() argument 4712 gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) gfx_v10_0_tcp_harvest() argument 4782 gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) gfx_v10_0_get_tcc_info() argument 4793 gfx_v10_0_constants_init(struct amdgpu_device *adev) gfx_v10_0_constants_init() argument 4830 gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) gfx_v10_0_enable_gui_idle_interrupt() argument 4852 gfx_v10_0_init_csb(struct amdgpu_device *adev) gfx_v10_0_init_csb() argument 4873 gfx_v10_0_rlc_stop(struct amdgpu_device *adev) gfx_v10_0_rlc_stop() argument 4881 gfx_v10_0_rlc_reset(struct amdgpu_device *adev) gfx_v10_0_rlc_reset() argument 4889 gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, bool enable) gfx_v10_0_rlc_smu_handshake_cntl() argument 4911 gfx_v10_0_rlc_start(struct amdgpu_device *adev) gfx_v10_0_rlc_start() argument 4922 gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) gfx_v10_0_rlc_enable_srm() argument 4933 gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) gfx_v10_0_rlc_load_microcode() argument 4961 gfx_v10_0_rlc_resume(struct amdgpu_device *adev) gfx_v10_0_rlc_resume() argument 5020 gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) gfx_v10_0_parse_rlc_toc() argument 5057 gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) gfx_v10_0_calc_toc_total_size() argument 5080 gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_buffer_init() argument 5100 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_buffer_fini() argument 5110 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, FIRMWARE_ID id, const void *fw_data, uint32_t fw_size) gfx_v10_0_rlc_backdoor_autoload_copy_ucode() argument 5137 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode() argument 5150 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode() argument 5211 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode() argument 5245 gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_enable() argument 5278 gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_config_me_cache() argument 5315 gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_config_ce_cache() argument 5352 gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache() argument 5389 gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_config_mec_cache() argument 5426 gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) gfx_v10_0_wait_for_rlc_autoload_complete() argument 5469 gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) gfx_v10_0_cp_gfx_enable() argument 5496 gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) gfx_v10_0_cp_gfx_load_pfp_microcode() argument 5574 gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) gfx_v10_0_cp_gfx_load_ce_microcode() argument 5651 gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) gfx_v10_0_cp_gfx_load_me_microcode() argument 5728 gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) gfx_v10_0_cp_gfx_load_microcode() argument 5758 gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) gfx_v10_0_cp_gfx_start() argument 5838 gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, CP_PIPE_ID pipe) gfx_v10_0_cp_gfx_switch_pipe() argument 5849 gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, struct amdgpu_ring *ring) gfx_v10_0_cp_gfx_set_doorbell() argument 5886 gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) gfx_v10_0_cp_gfx_resume() argument 5995 gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) gfx_v10_0_cp_compute_enable() argument 6026 gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) gfx_v10_0_cp_compute_load_microcode() argument 6099 struct amdgpu_device *adev = ring->adev; gfx_v10_0_kiq_setting() local 6125 struct amdgpu_device *adev = ring->adev; gfx_v10_0_gfx_mqd_init() local 6213 struct amdgpu_device *adev = ring->adev; gfx_v10_0_gfx_queue_init_register() local 6261 struct amdgpu_device *adev = ring->adev; gfx_v10_0_gfx_init_queue() local 6300 gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) gfx_v10_0_kiq_enable_kgq() argument 6323 gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) gfx_v10_0_cp_async_gfx_ring_resume() argument 6364 struct amdgpu_device *adev = ring->adev; gfx_v10_0_compute_mqd_set_priority() local 6378 struct amdgpu_device *adev = ring->adev; gfx_v10_0_compute_mqd_init() local 6515 struct amdgpu_device *adev = ring->adev; gfx_v10_0_kiq_init_register() local 6625 struct amdgpu_device *adev = ring->adev; gfx_v10_0_kiq_init_queue() local 6663 struct amdgpu_device *adev = ring->adev; gfx_v10_0_kcq_init_queue() local 6693 gfx_v10_0_kiq_resume(struct amdgpu_device *adev) gfx_v10_0_kiq_resume() argument 6718 gfx_v10_0_kcq_resume(struct amdgpu_device *adev) gfx_v10_0_kcq_resume() argument 6747 gfx_v10_0_cp_resume(struct amdgpu_device *adev) gfx_v10_0_cp_resume() argument 6801 gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) gfx_v10_0_cp_enable() argument 6807 gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) gfx_v10_0_check_grbm_cam_remapping() argument 6844 gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) gfx_v10_0_setup_grbm_cam_remapping() argument 6973 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_hw_init() local 7024 gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) gfx_v10_0_kiq_disable_kgq() argument 7047 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_hw_fini() local 7093 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_is_idle() local 7106 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_wait_for_idle() local 7124 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_soft_reset() local 7197 gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) gfx_v10_0_get_gpu_clock_counter() argument 7216 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_emit_gds_switch() local 7241 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_early_init() local 7270 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_late_init() local 7284 gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) gfx_v10_0_is_rlc_enabled() argument 7293 gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) gfx_v10_0_set_safe_mode() argument 7328 gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) gfx_v10_0_unset_safe_mode() argument 7344 gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable) gfx_v10_0_update_medium_grain_clock_gating() argument 7411 gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, bool enable) gfx_v10_0_update_3d_clock_gating() argument 7453 gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, bool enable) gfx_v10_0_update_coarse_grain_clock_gating() argument 7496 gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, bool enable) gfx_v10_0_update_gfx_clock_gating() argument 7534 gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) gfx_v10_0_update_spm_vmid() argument 7553 gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, uint32_t offset, struct soc15_reg_rlcg *entries, int arr_size) gfx_v10_0_check_rlcg_range() argument 7575 gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) gfx_v10_0_is_rlcg_access_range() argument 7613 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_set_powergating_state() local 7636 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_set_clockgating_state() local 7658 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_get_clockgating_state() local 7702 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_get_wptr_gfx() local 7718 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_set_wptr_gfx() local 7749 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_set_wptr_compute() local 7762 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_emit_hdp_flush() local 7920 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_emit_fence_kiq() local 8014 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_preempt_ib() local 8060 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_emit_ce_meta() local 8090 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_emit_de_meta() local 8134 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_emit_rreg() local 8182 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_emit_reg_write_reg_wait() local 8198 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_soft_recovery() local 8209 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, uint32_t me, uint32_t pipe, enum amdgpu_interrupt_state state) gfx_v10_0_set_gfx_eop_interrupt_state() argument 8250 gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, int me, int pipe, enum amdgpu_interrupt_state state) gfx_v10_0_set_compute_eop_interrupt_state() argument 8303 gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type, enum amdgpu_interrupt_state state) gfx_v10_0_set_eop_interrupt_state() argument 8345 gfx_v10_0_eop_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) gfx_v10_0_eop_irq() argument 8380 gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) gfx_v10_0_set_priv_reg_fault_state() argument 8399 gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) gfx_v10_0_set_priv_inst_fault_state() argument 8417 gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry) gfx_v10_0_handle_priv_fault() argument 8451 gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) gfx_v10_0_priv_reg_irq() argument 8460 gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) gfx_v10_0_priv_inst_irq() argument 8469 gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned int type, enum amdgpu_interrupt_state state) gfx_v10_0_kiq_set_interrupt_state() argument 8514 gfx_v10_0_kiq_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) gfx_v10_0_kiq_irq() argument 8694 gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) gfx_v10_0_set_ring_funcs() argument 8727 gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) gfx_v10_0_set_irq_funcs() argument 8742 gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) gfx_v10_0_set_rlc_funcs() argument 8759 gfx_v10_0_set_gds_init(struct amdgpu_device *adev) gfx_v10_0_set_gds_init() argument 8771 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, u32 bitmap) gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh() argument 8785 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) gfx_v10_0_get_wgp_active_bitmap_per_sh() argument 8800 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) gfx_v10_0_get_cu_active_bitmap_per_sh() argument 8818 gfx_v10_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info) gfx_v10_0_get_cu_info() argument 8871 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) gfx_v10_3_get_disabled_sa() argument 8891 gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) gfx_v10_3_program_pbb_mode() argument [all...]
H A D	gfx_v9_0.c	739 static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v) in gfx_v9_0_rlcg_wreg() argument 833 struct amdgpu_device *adev = kiq_ring->adev; gfx_v9_0_kiq_map_queues() local 935 gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) gfx_v9_0_set_kiq_pm4_funcs() argument 940 gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) gfx_v9_0_init_golden_registers() argument 998 gfx_v9_0_scratch_init(struct amdgpu_device *adev) gfx_v9_0_scratch_init() argument 1041 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_test_ring() local 1078 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_test_ib() local 1133 gfx_v9_0_free_microcode(struct amdgpu_device *adev) gfx_v9_0_free_microcode() argument 1151 gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev) gfx_v9_0_init_rlc_ext_microcode() argument 1172 gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) gfx_v9_0_check_fw_write_wait() argument 1273 is_raven_kicker(struct amdgpu_device *adev) is_raven_kicker() argument 1281 check_if_enlarge_doorbell_range(struct amdgpu_device *adev) check_if_enlarge_doorbell_range() argument 1291 gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) gfx_v9_0_check_if_need_gfxoff() argument 1326 gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, const char *chip_name) gfx_v9_0_init_cp_gfx_microcode() argument 1406 gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, const char *chip_name) gfx_v9_0_init_rlc_microcode() argument 1537 gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, const char *chip_name) gfx_v9_0_init_cp_compute_microcode() argument 1628 gfx_v9_0_init_microcode(struct amdgpu_device *adev) gfx_v9_0_init_microcode() argument 1684 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) gfx_v9_0_get_csb_size() argument 1712 gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer) gfx_v9_0_get_csb_buffer() argument 1753 gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev) gfx_v9_0_init_always_on_cu_mask() argument 1797 gfx_v9_0_init_lbpw(struct amdgpu_device *adev) gfx_v9_0_init_lbpw() argument 1846 gfx_v9_4_init_lbpw(struct amdgpu_device *adev) gfx_v9_4_init_lbpw() argument 1895 gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_lbpw() argument 1900 gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) gfx_v9_0_cp_jump_table_num() argument 1905 gfx_v9_0_rlc_init(struct amdgpu_device *adev) gfx_v9_0_rlc_init() argument 1947 gfx_v9_0_mec_fini(struct amdgpu_device *adev) gfx_v9_0_mec_fini() argument 1953 gfx_v9_0_mec_init(struct amdgpu_device *adev) gfx_v9_0_mec_init() argument 2013 wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) wave_read_ind() argument 2023 wave_read_regs(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t regno, uint32_t num, uint32_t *out) wave_read_regs() argument 2038 gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) gfx_v9_0_read_wave_data() argument 2058 gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) gfx_v9_0_read_wave_sgprs() argument 2067 gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst) gfx_v9_0_read_wave_vgprs() argument 2077 gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, u32 me, u32 pipe, u32 q, u32 vm) gfx_v9_0_select_me_pipe_q() argument 2108 gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) gfx_v9_0_gpu_early_init() argument 2224 gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, int mec, int pipe, int queue) gfx_v9_0_compute_ring_init() argument 2261 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_sw_init() local 2397 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_sw_fini() local 2423 gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) gfx_v9_0_tiling_mode_table_init() argument 2428 gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) gfx_v9_0_select_se_sh() argument 2451 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) gfx_v9_0_get_rb_active_bitmap() argument 2467 gfx_v9_0_setup_rb(struct amdgpu_device *adev) gfx_v9_0_setup_rb() argument 2492 gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) gfx_v9_0_init_compute_vmid() argument 2530 gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev) gfx_v9_0_init_gds_vmid() argument 2548 gfx_v9_0_init_sq_config(struct amdgpu_device *adev) gfx_v9_0_init_sq_config() argument 2564 gfx_v9_0_constants_init(struct amdgpu_device *adev) gfx_v9_0_constants_init() argument 2613 gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) gfx_v9_0_wait_for_rlc_serdes() argument 2651 gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_gui_idle_interrupt() argument 2664 gfx_v9_0_init_csb(struct amdgpu_device *adev) gfx_v9_0_init_csb() argument 2713 gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev) gfx_v9_1_init_rlc_save_restore_list() argument 2816 gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) gfx_v9_0_enable_save_restore_machine() argument 2821 pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, bool enable) pwr_10_0_gfxip_control_over_cgpg() argument 2847 gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) gfx_v9_0_init_gfx_power_gating() argument 2889 gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_sck_slow_down_on_power_up() argument 2903 gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_sck_slow_down_on_power_down() argument 2917 gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_cp_power_gating() argument 2931 gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_gfx_cg_power_gating() argument 2944 gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_gfx_pipeline_powergating() argument 2961 gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_gfx_static_mg_power_gating() argument 2974 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_gfx_dynamic_mg_power_gating() argument 2987 gfx_v9_0_init_pg(struct amdgpu_device *adev) gfx_v9_0_init_pg() argument 3014 gfx_v9_0_rlc_stop(struct amdgpu_device *adev) gfx_v9_0_rlc_stop() argument 3021 gfx_v9_0_rlc_reset(struct amdgpu_device *adev) gfx_v9_0_rlc_reset() argument 3029 gfx_v9_0_rlc_start(struct amdgpu_device *adev) gfx_v9_0_rlc_start() argument 3061 gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) gfx_v9_0_rlc_load_microcode() argument 3086 gfx_v9_0_rlc_resume(struct amdgpu_device *adev) gfx_v9_0_rlc_resume() argument 3131 gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) gfx_v9_0_cp_gfx_enable() argument 3142 gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) gfx_v9_0_cp_gfx_load_microcode() argument 3199 gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) gfx_v9_0_cp_gfx_start() argument 3261 gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) gfx_v9_0_cp_gfx_resume() argument 3331 gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) gfx_v9_0_cp_compute_enable() argument 3343 gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) gfx_v9_0_cp_compute_load_microcode() argument 3389 struct amdgpu_device *adev = ring->adev; gfx_v9_0_kiq_setting() local 3402 struct amdgpu_device *adev = ring->adev; gfx_v9_0_mqd_set_priority() local 3417 struct amdgpu_device *adev = ring->adev; gfx_v9_0_mqd_init() local 3566 struct amdgpu_device *adev = ring->adev; gfx_v9_0_kiq_init_register() local 3680 struct amdgpu_device *adev = ring->adev; gfx_v9_0_kiq_fini_register() local 3719 struct amdgpu_device *adev = ring->adev; gfx_v9_0_kiq_init_queue() local 3759 struct amdgpu_device *adev = ring->adev; gfx_v9_0_kcq_init_queue() local 3791 gfx_v9_0_kiq_resume(struct amdgpu_device *adev) gfx_v9_0_kiq_resume() argument 3816 gfx_v9_0_kcq_resume(struct amdgpu_device *adev) gfx_v9_0_kcq_resume() argument 3845 gfx_v9_0_cp_resume(struct amdgpu_device *adev) gfx_v9_0_cp_resume() argument 3897 gfx_v9_0_init_tcp_config(struct amdgpu_device *adev) gfx_v9_0_init_tcp_config() argument 3914 gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) gfx_v9_0_cp_enable() argument 3924 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_hw_init() local 3946 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_hw_fini() local 4000 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_is_idle() local 4012 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_wait_for_idle() local 4026 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_soft_reset() local 4085 gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) gfx_v9_0_kiq_read_clock() argument 4159 gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) gfx_v9_0_get_gpu_clock_counter() argument 4202 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_emit_gds_switch() local 4461 gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev) gfx_v9_0_do_edc_gds_workarounds() argument 4508 gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) gfx_v9_0_do_edc_gpr_workarounds() argument 4682 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_early_init() local 4700 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_ecc_late_init() local 4733 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_late_init() local 4751 gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev) gfx_v9_0_is_rlc_enabled() argument 4763 gfx_v9_0_set_safe_mode(struct amdgpu_device *adev) gfx_v9_0_set_safe_mode() argument 4780 gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev) gfx_v9_0_unset_safe_mode() argument 4788 gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_update_gfx_cg_power_gating() argument 4806 gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_update_gfx_mg_power_gating() argument 4825 gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_update_medium_grain_clock_gating() argument 4900 gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_update_3d_clock_gating() argument 4955 gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_update_coarse_grain_clock_gating() argument 5007 gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_update_gfx_clock_gating() argument 5032 gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) gfx_v9_0_update_spm_vmid() argument 5051 gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev, uint32_t offset, struct soc15_reg_rlcg *entries, int arr_size) gfx_v9_0_check_rlcg_range() argument 5073 gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) gfx_v9_0_is_rlcg_access_range() argument 5100 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_set_powergating_state() local 5144 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_set_clockgating_state() local 5167 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_get_clockgating_state() local 5216 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_get_wptr_gfx() local 5232 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_set_wptr_gfx() local 5246 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_emit_hdp_flush() local 5418 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_set_wptr_compute() local 5432 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_emit_fence_kiq() local 5572 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_emit_rreg() local 5620 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_emit_reg_write_reg_wait() local 5634 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_soft_recovery() local 5644 gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, enum amdgpu_interrupt_state state) gfx_v9_0_set_gfx_eop_interrupt_state() argument 5659 gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, int me, int pipe, enum amdgpu_interrupt_state state) gfx_v9_0_set_compute_eop_interrupt_state() argument 5712 gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) gfx_v9_0_set_priv_reg_fault_state() argument 5731 gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) gfx_v9_0_set_priv_inst_fault_state() argument 5757 gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) gfx_v9_0_set_cp_ecc_error_state() argument 5788 gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type, enum amdgpu_interrupt_state state) gfx_v9_0_set_eop_interrupt_state() argument 5827 gfx_v9_0_eop_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) gfx_v9_0_eop_irq() argument 5859 gfx_v9_0_fault(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry) gfx_v9_0_fault() argument 5886 gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) gfx_v9_0_priv_reg_irq() argument 5895 gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) gfx_v9_0_priv_inst_irq() argument 6346 gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, void *inject_if) gfx_v9_0_ras_error_inject() argument 6463 gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, struct ras_err_data *err_data) gfx_v9_0_query_utc_edc_status() argument 6560 gfx_v9_0_ras_error_count(struct amdgpu_device *adev, const struct soc15_reg_entry *reg, uint32_t se_id, uint32_t inst_id, uint32_t value, uint32_t *sec_count, uint32_t *ded_count) gfx_v9_0_ras_error_count() argument 6602 gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev) gfx_v9_0_reset_ras_error_count() argument 6657 gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status) gfx_v9_0_query_ras_error_count() argument 6854 gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) gfx_v9_0_set_ring_funcs() argument 6888 gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) gfx_v9_0_set_irq_funcs() argument 6903 gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) gfx_v9_0_set_rlc_funcs() argument 6919 gfx_v9_0_set_gds_init(struct amdgpu_device *adev) gfx_v9_0_set_gds_init() argument 6964 gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, u32 bitmap) gfx_v9_0_set_user_cu_inactive_bitmap() argument 6978 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) gfx_v9_0_get_cu_active_bitmap() argument 6993 gfx_v9_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info) gfx_v9_0_get_cu_info() argument [all...]
H A D	amdgpu.h	114 struct amdgpu_device *adev; member 425 struct amdgpu_device *adev; member 497 struct amdgpu_device *adev; global() member 1007 adev_to_drm(struct amdgpu_device *adev) adev_to_drm() argument 1269 amdgpu_acpi_init(struct amdgpu_device *adev) amdgpu_acpi_init() argument 1270 amdgpu_acpi_fini(struct amdgpu_device *adev) amdgpu_acpi_fini() argument 1280 amdgpu_dm_display_resume(struct amdgpu_device *adev) amdgpu_dm_display_resume() argument 1311 amdgpu_is_tmz(struct amdgpu_device *adev) amdgpu_is_tmz() argument 1316 amdgpu_in_reset(struct amdgpu_device *adev) amdgpu_in_reset() argument [all...]
/kernel/linux/linux-5.10/drivers/dma/
H A D	pl330.c	3011 pl330_probe(struct amba_device *adev, const struct amba_id *id) in pl330_probe() argument 3216 pl330_remove(struct amba_device *adev) pl330_remove() argument [all...]
/kernel/linux/linux-5.10/drivers/ata/
H A D	sata_mv.c	1405 static void mv6_dev_config(struct ata_device *adev) in mv6_dev_config() argument
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/
H A D	si_dpm.c	1837 si_get_pi(struct amdgpu_device *adev) si_get_pi() argument 1870 si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev, const struct ni_leakage_coeffients *coeff, u16 v, s32 t, u32 i_leakage, u32 *leakage) si_calculate_leakage_for_v_and_t() argument 1898 si_calculate_leakage_for_v(struct amdgpu_device *adev, const struct ni_leakage_coeffients *coeff, const u32 fixed_kt, u16 v, u32 i_leakage, u32 *leakage) si_calculate_leakage_for_v() argument 1909 si_update_dte_from_pl2(struct amdgpu_device *adev, struct si_dte_data *dte_data) si_update_dte_from_pl2() argument 1939 rv770_get_pi(struct amdgpu_device *adev) rv770_get_pi() argument 1946 ni_get_pi(struct amdgpu_device *adev) ni_get_pi() argument 1960 si_initialize_powertune_defaults(struct amdgpu_device *adev) si_initialize_powertune_defaults() argument 2164 si_get_smc_power_scaling_factor(struct amdgpu_device *adev) si_get_smc_power_scaling_factor() argument 2169 si_calculate_cac_wintime(struct amdgpu_device *adev) si_calculate_cac_wintime() argument 2194 si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev, bool adjust_polarity, u32 tdp_adjustment, u32 *tdp_limit, u32 *near_tdp_limit) si_calculate_adjusted_tdp_limits() argument 2227 si_populate_smc_tdp_limits(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state) si_populate_smc_tdp_limits() argument 2292 si_populate_smc_tdp_limits_2(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state) si_populate_smc_tdp_limits_2() argument 2324 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev, const u16 prev_std_vddc, const u16 curr_std_vddc) si_calculate_power_efficiency_ratio() argument 2346 si_should_disable_uvd_powertune(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state) si_should_disable_uvd_powertune() argument 2358 evergreen_get_pi(struct amdgpu_device *adev) evergreen_get_pi() argument 2365 si_populate_power_containment_values(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SISLANDS_SMC_SWSTATE *smc_state) si_populate_power_containment_values() argument 2458 si_populate_sq_ramping_values(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SISLANDS_SMC_SWSTATE *smc_state) si_populate_sq_ramping_values() argument 2515 si_enable_power_containment(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state, bool enable) si_enable_power_containment() argument 2545 si_initialize_smc_dte_tables(struct amdgpu_device *adev) si_initialize_smc_dte_tables() argument 2612 si_get_cac_std_voltage_max_min(struct amdgpu_device *adev, u16 *max, u16 *min) si_get_cac_std_voltage_max_min() argument 2656 si_init_dte_leakage_table(struct amdgpu_device *adev, PP_SIslands_CacConfig *cac_tables, u16 vddc_max, u16 vddc_min, u16 vddc_step, u16 t0, u16 t_step) si_init_dte_leakage_table() argument 2696 si_init_simplified_leakage_table(struct amdgpu_device *adev, PP_SIslands_CacConfig *cac_tables, u16 vddc_max, u16 vddc_min, u16 vddc_step) si_init_simplified_leakage_table() argument 2731 si_initialize_smc_cac_tables(struct amdgpu_device *adev) si_initialize_smc_cac_tables() argument 2817 si_program_cac_config_registers(struct amdgpu_device *adev, const struct si_cac_config_reg *cac_config_regs) si_program_cac_config_registers() argument 2856 si_initialize_hardware_cac_manager(struct amdgpu_device *adev) si_initialize_hardware_cac_manager() argument 2879 si_enable_smc_cac(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state, bool enable) si_enable_smc_cac() argument 2926 si_init_smc_spll_table(struct amdgpu_device *adev) si_init_smc_spll_table() argument 2997 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev, u16 vce_voltage) si_get_lower_of_leakage_and_vce_voltage() argument 3015 si_get_vce_clock_voltage(struct amdgpu_device *adev, u32 evclk, u32 ecclk, u16 *voltage) si_get_vce_clock_voltage() argument 3049 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_vblank_too_short() local 3061 ni_copy_and_switch_arb_sets(struct amdgpu_device *adev, u32 arb_freq_src, u32 arb_freq_dest) ni_copy_and_switch_arb_sets() argument 3126 ni_update_current_ps(struct amdgpu_device *adev, struct amdgpu_ps *rps) ni_update_current_ps() argument 3139 ni_update_requested_ps(struct amdgpu_device *adev, struct amdgpu_ps *rps) ni_update_requested_ps() argument 3152 ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev, struct amdgpu_ps *new_ps, struct amdgpu_ps *old_ps) ni_set_uvd_clock_before_set_eng_clock() argument 3170 ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev, struct amdgpu_ps *new_ps, struct amdgpu_ps *old_ps) ni_set_uvd_clock_after_set_eng_clock() argument 3216 btc_get_valid_mclk(struct amdgpu_device *adev, u32 max_mclk, u32 requested_mclk) btc_get_valid_mclk() argument 3223 btc_get_valid_sclk(struct amdgpu_device *adev, u32 max_sclk, u32 requested_sclk) btc_get_valid_sclk() argument 3267 btc_adjust_clock_combinations(struct amdgpu_device *adev, const struct amdgpu_clock_and_voltage_limits *max_limits, struct rv7xx_pl *pl) btc_adjust_clock_combinations() argument 3294 btc_apply_voltage_delta_rules(struct amdgpu_device *adev, u16 max_vddc, u16 max_vddci, u16 *vddc, u16 *vddci) btc_apply_voltage_delta_rules() argument 3374 rv770_get_memory_module_index(struct amdgpu_device *adev) rv770_get_memory_module_index() argument 3379 rv770_get_max_vddc(struct amdgpu_device *adev) rv770_get_max_vddc() argument 3390 rv770_get_engine_memory_ss(struct amdgpu_device *adev) rv770_get_engine_memory_ss() argument 3407 si_apply_state_adjust_rules(struct amdgpu_device *adev, struct amdgpu_ps *rps) si_apply_state_adjust_rules() argument 3633 si_write_smc_soft_register(struct amdgpu_device *adev, u16 reg_offset, u32 value) si_write_smc_soft_register() argument 3643 si_is_special_1gb_platform(struct amdgpu_device *adev) si_is_special_1gb_platform() argument 3671 si_get_leakage_vddc(struct amdgpu_device *adev) si_get_leakage_vddc() argument 3690 si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev, u32 index, u16 *leakage_voltage) si_get_leakage_voltage_from_leakage_index() argument 3717 si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources) si_set_dpm_event_sources() argument 3752 si_enable_auto_throttle_source(struct amdgpu_device *adev, enum amdgpu_dpm_auto_throttle_src source, bool enable) si_enable_auto_throttle_source() argument 3771 si_start_dpm(struct amdgpu_device *adev) si_start_dpm() argument 3776 si_stop_dpm(struct amdgpu_device *adev) si_stop_dpm() argument 3781 si_enable_sclk_control(struct amdgpu_device *adev, bool enable) si_enable_sclk_control() argument 3823 si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, PPSMC_Msg msg, u32 parameter) si_send_msg_to_smc_with_parameter() argument 3830 si_restrict_performance_levels_before_switch(struct amdgpu_device *adev) si_restrict_performance_levels_before_switch() argument 3842 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_force_performance_level() local 3880 si_set_sw_state(struct amdgpu_device *adev) si_set_sw_state() argument 3886 si_halt_smc(struct amdgpu_device *adev) si_halt_smc() argument 3895 si_resume_smc(struct amdgpu_device *adev) si_resume_smc() argument 3904 si_dpm_start_smc(struct amdgpu_device *adev) si_dpm_start_smc() argument 3911 si_dpm_stop_smc(struct amdgpu_device *adev) si_dpm_stop_smc() argument 3917 si_process_firmware_header(struct amdgpu_device *adev) si_process_firmware_header() argument 4007 si_read_clock_registers(struct amdgpu_device *adev) si_read_clock_registers() argument 4028 si_enable_thermal_protection(struct amdgpu_device *adev, bool enable) si_enable_thermal_protection() argument 4037 si_enable_acpi_power_management(struct amdgpu_device *adev) si_enable_acpi_power_management() argument 4070 si_notify_smc_display_change(struct amdgpu_device *adev, bool has_display) si_notify_smc_display_change() argument 4080 si_program_response_times(struct amdgpu_device *adev) si_program_response_times() argument 4108 si_program_ds_registers(struct amdgpu_device *adev) si_program_ds_registers() argument 4126 si_program_display_gap(struct amdgpu_device *adev) si_program_display_gap() argument 4171 si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable) si_enable_spread_spectrum() argument 4184 si_setup_bsp(struct amdgpu_device *adev) si_setup_bsp() argument 4208 si_program_git(struct amdgpu_device *adev) si_program_git() argument 4213 si_program_tp(struct amdgpu_device *adev) si_program_tp() argument 4233 si_program_tpp(struct amdgpu_device *adev) si_program_tpp() argument 4238 si_program_sstp(struct amdgpu_device *adev) si_program_sstp() argument 4243 si_enable_display_gap(struct amdgpu_device *adev) si_enable_display_gap() argument 4257 si_program_vc(struct amdgpu_device *adev) si_program_vc() argument 4264 si_clear_vc(struct amdgpu_device *adev) si_clear_vc() argument 4304 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk) si_get_strobe_mode_settings() argument 4324 si_upload_firmware(struct amdgpu_device *adev) si_upload_firmware() argument 4334 si_validate_phase_shedding_tables(struct amdgpu_device *adev, const struct atom_voltage_table *table, const struct amdgpu_phase_shedding_limits_table *limits) si_validate_phase_shedding_tables() argument 4361 si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev, u32 max_voltage_steps, struct atom_voltage_table *voltage_table) si_trim_voltage_table_to_fit_state_table() argument 4378 si_get_svi2_voltage_table(struct amdgpu_device *adev, struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table, struct atom_voltage_table *voltage_table) si_get_svi2_voltage_table() argument 4399 si_construct_voltage_tables(struct amdgpu_device *adev) si_construct_voltage_tables() argument 4479 si_populate_smc_voltage_table(struct amdgpu_device *adev, const struct atom_voltage_table *voltage_table, SISLANDS_SMC_STATETABLE *table) si_populate_smc_voltage_table() argument 4489 si_populate_smc_voltage_tables(struct amdgpu_device *adev, SISLANDS_SMC_STATETABLE *table) si_populate_smc_voltage_tables() argument 4552 si_populate_voltage_value(struct amdgpu_device *adev, const struct atom_voltage_table *table, u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) si_populate_voltage_value() argument 4572 si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk, SISLANDS_SMC_VOLTAGE_VALUE *voltage) si_populate_mvdd_value() argument 4589 si_get_std_voltage_value(struct amdgpu_device *adev, SISLANDS_SMC_VOLTAGE_VALUE *voltage, u16 *std_voltage) si_get_std_voltage_value() argument 4640 si_populate_std_voltage_value(struct amdgpu_device *adev, u16 value, u8 index, SISLANDS_SMC_VOLTAGE_VALUE *voltage) si_populate_std_voltage_value() argument 4650 si_populate_phase_shedding_value(struct amdgpu_device *adev, const struct amdgpu_phase_shedding_limits_table *limits, u16 voltage, u32 sclk, u32 mclk, SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) si_populate_phase_shedding_value() argument 4669 si_init_arb_table_index(struct amdgpu_device *adev) si_init_arb_table_index() argument 4687 si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev) si_initial_switch_from_arb_f0_to_f1() argument 4692 si_reset_to_default(struct amdgpu_device *adev) si_reset_to_default() argument 4698 si_force_switch_to_arb_f0(struct amdgpu_device *adev) si_force_switch_to_arb_f0() argument 4717 si_calculate_memory_refresh_rate(struct amdgpu_device *adev, u32 engine_clock) si_calculate_memory_refresh_rate() argument 4736 si_populate_memory_timing_parameters(struct amdgpu_device *adev, struct rv7xx_pl *pl, SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) si_populate_memory_timing_parameters() argument 4762 si_do_program_memory_timing_parameters(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, unsigned int first_arb_set) si_do_program_memory_timing_parameters() argument 4789 si_program_memory_timing_parameters(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state) si_program_memory_timing_parameters() argument 4796 si_populate_initial_mvdd_value(struct amdgpu_device *adev, struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) si_populate_initial_mvdd_value() argument 4809 si_populate_smc_initial_state(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_initial_state, SISLANDS_SMC_STATETABLE *table) si_populate_smc_initial_state() argument 4930 si_populate_smc_acpi_state(struct amdgpu_device *adev, SISLANDS_SMC_STATETABLE *table) si_populate_smc_acpi_state() argument 5072 si_populate_ulv_state(struct amdgpu_device *adev, SISLANDS_SMC_SWSTATE *state) si_populate_ulv_state() argument 5103 si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev) si_program_ulv_memory_timing_parameters() argument 5129 si_get_mvdd_configuration(struct amdgpu_device *adev) si_get_mvdd_configuration() argument 5136 si_init_smc_table(struct amdgpu_device *adev) si_init_smc_table() argument 5223 si_calculate_sclk_params(struct amdgpu_device *adev, u32 engine_clock, SISLANDS_SMC_SCLK_VALUE *sclk) si_calculate_sclk_params() argument 5293 si_populate_sclk_value(struct amdgpu_device *adev, u32 engine_clock, SISLANDS_SMC_SCLK_VALUE *sclk) si_populate_sclk_value() argument 5314 si_populate_mclk_value(struct amdgpu_device *adev, u32 engine_clock, u32 memory_clock, SISLANDS_SMC_MCLK_VALUE *mclk, bool strobe_mode, bool dll_state_on) si_populate_mclk_value() argument 5403 si_populate_smc_sp(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SISLANDS_SMC_SWSTATE *smc_state) si_populate_smc_sp() argument 5418 si_convert_power_level_to_smc(struct amdgpu_device *adev, struct rv7xx_pl *pl, SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) si_convert_power_level_to_smc() argument 5527 si_populate_smc_t(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SISLANDS_SMC_SWSTATE *smc_state) si_populate_smc_t() argument 5576 si_disable_ulv(struct amdgpu_device *adev) si_disable_ulv() argument 5588 si_is_state_ulv_compatible(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state) si_is_state_ulv_compatible() argument 5616 si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state) si_set_power_state_conditionally_enable_ulv() argument 5630 si_convert_power_state_to_smc(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SISLANDS_SMC_SWSTATE *smc_state) si_convert_power_state_to_smc() argument 5710 si_upload_sw_state(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state) si_upload_sw_state() argument 5733 si_upload_ulv_state(struct amdgpu_device *adev) si_upload_ulv_state() argument 5756 si_upload_smc_data(struct amdgpu_device *adev) si_upload_smc_data() argument 5795 si_set_mc_special_registers(struct amdgpu_device *adev, struct si_mc_reg_table *table) si_set_mc_special_registers() argument 5966 si_initialize_mc_reg_table(struct amdgpu_device *adev) si_initialize_mc_reg_table() argument 6016 si_populate_mc_reg_addresses(struct amdgpu_device *adev, SMC_SIslands_MCRegisters *mc_reg_table) si_populate_mc_reg_addresses() argument 6050 si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev, struct rv7xx_pl *pl, SMC_SIslands_MCRegisterSet *mc_reg_table_data) si_convert_mc_reg_table_entry_to_smc() argument 6070 si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SMC_SIslands_MCRegisters *mc_reg_table) si_convert_mc_reg_table_to_smc() argument 6084 si_populate_mc_reg_table(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_boot_state) si_populate_mc_reg_table() argument 6122 si_upload_mc_reg_table(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state) si_upload_mc_reg_table() argument 6142 si_enable_voltage_control(struct amdgpu_device *adev, bool enable) si_enable_voltage_control() argument 6150 si_get_maximum_link_speed(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state) si_get_maximum_link_speed() argument 6165 si_get_current_pcie_speed(struct amdgpu_device *adev) si_get_current_pcie_speed() argument 6175 si_request_link_speed_change_before_state_change(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state, struct amdgpu_ps *amdgpu_current_state) si_request_link_speed_change_before_state_change() argument 6215 si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state, struct amdgpu_ps *amdgpu_current_state) si_notify_link_speed_change_after_state_change() argument 6260 si_set_max_cu_value(struct amdgpu_device *adev) si_set_max_cu_value() argument 6301 si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev, struct amdgpu_clock_voltage_dependency_table *table) si_patch_single_dependency_table_based_on_leakage() argument 6332 si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev) si_patch_dependency_tables_based_on_leakage() argument 6351 si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state, struct amdgpu_ps *amdgpu_current_state) si_set_pcie_lane_width_in_smc() argument 6368 si_dpm_setup_asic(struct amdgpu_device *adev) si_dpm_setup_asic() argument 6374 si_thermal_enable_alert(struct amdgpu_device *adev, bool enable) si_thermal_enable_alert() argument 6397 si_thermal_set_temperature_range(struct amdgpu_device *adev, int min_temp, int max_temp) si_thermal_set_temperature_range() argument 6422 si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode) si_fan_ctrl_set_static_mode() argument 6444 si_thermal_setup_fan_table(struct amdgpu_device *adev) si_thermal_setup_fan_table() argument 6513 si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev) si_fan_ctrl_start_smc_fan_control() argument 6527 si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev) si_fan_ctrl_stop_smc_fan_control() argument 6547 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_get_fan_speed_percent() local 6571 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_set_fan_speed_percent() local 6604 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_set_fan_control_mode() local 6622 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_get_fan_control_mode() local 6685 si_fan_ctrl_set_default_mode(struct amdgpu_device *adev) si_fan_ctrl_set_default_mode() argument 6702 si_thermal_start_smc_fan_control(struct amdgpu_device *adev) si_thermal_start_smc_fan_control() argument 6710 si_thermal_initialize(struct amdgpu_device *adev) si_thermal_initialize() argument 6725 si_thermal_start_thermal_controller(struct amdgpu_device *adev) si_thermal_start_thermal_controller() argument 6752 si_thermal_stop_thermal_controller(struct amdgpu_device *adev) si_thermal_stop_thermal_controller() argument 6760 si_dpm_enable(struct amdgpu_device *adev) si_dpm_enable() argument 6878 si_set_temperature_range(struct amdgpu_device *adev) si_set_temperature_range() argument 6895 si_dpm_disable(struct amdgpu_device *adev) si_dpm_disable() argument 6921 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_pre_set_power_state() local 6932 si_power_control_set_level(struct amdgpu_device *adev) si_power_control_set_level() argument 6958 si_set_vce_clock(struct amdgpu_device *adev, struct amdgpu_ps *new_rps, struct amdgpu_ps *old_rps) si_set_vce_clock() argument 6978 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_set_power_state() local 7082 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_post_set_power_state() local 7100 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_display_configuration_changed() local 7106 si_parse_pplib_non_clock_info(struct amdgpu_device *adev, struct amdgpu_ps *rps, struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, u8 table_rev) si_parse_pplib_non_clock_info() argument 7132 si_parse_pplib_clock_info(struct amdgpu_device *adev, struct amdgpu_ps *rps, int index, union pplib_clock_info *clock_info) si_parse_pplib_clock_info() argument 7213 si_parse_power_table(struct amdgpu_device *adev) si_parse_power_table() argument 7303 si_dpm_init(struct amdgpu_device *adev) si_dpm_init() argument 7466 si_dpm_fini(struct amdgpu_device *adev) si_dpm_fini() argument 7482 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_debugfs_print_current_performance_level() local 7501 si_dpm_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) si_dpm_set_interrupt_state() argument 7549 si_dpm_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) si_dpm_process_interrupt() argument 7582 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_late_init() local 7605 si_dpm_init_microcode(struct amdgpu_device *adev) si_dpm_init_microcode() argument 7688 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_sw_init() local 7737 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_sw_fini() local 7752 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_hw_init() local 7771 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_hw_fini() local 7784 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_suspend() local 7800 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_resume() local 7852 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_get_temp() local 7869 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_get_sclk() local 7881 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_get_mclk() local 7894 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_print_power_state() local 7918 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_early_init() local 7946 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_check_state_equal() local 7983 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_read_sensor() local 8073 si_dpm_set_irq_funcs(struct amdgpu_device *adev) si_dpm_set_irq_funcs() argument [all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/inc/
H A D	hwmgr.h	745 void *adev; member
/kernel/linux/linux-5.10/drivers/iommu/intel/
H A D	iommu.c	4938 struct acpi_device *adev; in probe_acpi_namespace_devices() local
/kernel/linux/linux-5.10/drivers/pci/
H A D	pci.c	6094 struct acpi_device *adev; in pci_pr3_present() local
/kernel/linux/linux-6.6/drivers/net/ethernet/mellanox/mlx5/core/
H A D	en_main.c	5982 static int mlx5e_resume(struct auxiliary_device *adev) in mlx5e_resume() argument 6007 static int mlx5e_suspend(struct auxiliary_device *adev, pm_message_t state) in mlx5e_suspend() argument 6025 static int mlx5e_probe(struct auxiliary_device *adev, in mlx5e_probe() argument 6100 mlx5e_remove(struct auxiliary_device *adev) mlx5e_remove() argument [all...]
/kernel/linux/linux-6.6/drivers/ata/
H A D	sata_mv.c	1401 static void mv6_dev_config(struct ata_device *adev) in mv6_dev_config() argument
/kernel/linux/linux-6.6/include/linux/mlx5/
H A D	driver.h	556 struct auxiliary_device adev; member 612 struct mlx5_adev **adev; member
/kernel/linux/linux-6.6/drivers/usb/typec/tcpm/
H A D	tcpm.c	1593 static int tcpm_pd_svdm(struct tcpm_port *port, struct typec_altmode *adev, in tcpm_pd_svdm() argument 1793 struct typec_altmode *adev; in tcpm_handle_vdm_request() local [all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A D	gfx_v9_4_3.c	81 struct amdgpu_device *adev = kiq_ring->adev; in gfx_v9_4_3_kiq_map_queues() local 183 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) in gfx_v9_4_3_set_kiq_pm4_funcs() argument 192 gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) gfx_v9_4_3_init_golden_registers() argument 250 struct amdgpu_device *adev = ring->adev; gfx_v9_4_3_ring_test_ring() local 283 struct amdgpu_device *adev = ring->adev; gfx_v9_4_3_ring_test_ib() local 339 gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) gfx_v9_4_3_get_gpu_clock_counter() argument 352 gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) gfx_v9_4_3_free_microcode() argument 364 gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, const char *chip_name) gfx_v9_4_3_init_rlc_microcode() argument 395 gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) gfx_v9_4_3_check_if_need_gfxoff() argument 401 gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, const char *chip_name) gfx_v9_4_3_init_cp_compute_microcode() argument 426 gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) gfx_v9_4_3_init_microcode() argument 444 gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) gfx_v9_4_3_mec_fini() argument 450 gfx_v9_4_3_mec_init(struct amdgpu_device *adev) gfx_v9_4_3_mec_init() argument 523 gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance, int xcc_id) gfx_v9_4_3_xcc_select_se_sh() argument 550 wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) wave_read_ind() argument 560 wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t regno, uint32_t num, uint32_t *out) wave_read_regs() argument 575 gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) gfx_v9_4_3_read_wave_data() argument 598 gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) gfx_v9_4_3_read_wave_sgprs() argument 606 gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst) gfx_v9_4_3_read_wave_vgprs() argument 615 gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) gfx_v9_4_3_select_me_pipe_q() argument 622 gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, int num_xccs_per_xcp) gfx_v9_4_3_switch_compute_partition() argument 654 gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) gfx_v9_4_3_ih_to_xcc_inst() argument 678 gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) gfx_v9_4_3_gpu_early_init() argument 739 gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, int xcc_id, int mec, int pipe, int queue) gfx_v9_4_3_compute_ring_init() argument 782 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_4_3_sw_init() local 880 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_4_3_sw_fini() local 902 gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_init_compute_vmid() argument 947 gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_init_gds_vmid() argument 965 gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_constants_init() argument 1011 gfx_v9_4_3_constants_init(struct amdgpu_device *adev) gfx_v9_4_3_constants_init() argument 1026 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_enable_save_restore_machine() argument 1032 gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_init_pg() argument 1042 gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_disable_gpa_mode() argument 1051 gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) gfx_v9_4_3_is_rlc_enabled() argument 1063 gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_set_safe_mode() argument 1080 gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_unset_safe_mode() argument 1089 gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) gfx_v9_4_3_init_rlcg_reg_access_ctrl() argument 1107 gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) gfx_v9_4_3_rlc_init() argument 1116 gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_wait_for_rlc_serdes() argument 1158 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable, int xcc_id) gfx_v9_4_3_xcc_enable_gui_idle_interrupt() argument 1174 gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_rlc_stop() argument 1182 gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) gfx_v9_4_3_rlc_stop() argument 1191 gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_rlc_reset() argument 1201 gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) gfx_v9_4_3_rlc_reset() argument 1210 gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_rlc_start() argument 1223 gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) gfx_v9_4_3_rlc_start() argument 1252 gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_rlc_load_microcode() argument 1283 gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_rlc_resume() argument 1305 gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) gfx_v9_4_3_rlc_resume() argument 1322 gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) gfx_v9_4_3_update_spm_vmid() argument 1347 gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, uint32_t offset, struct soc15_reg_rlcg *entries, int arr_size) gfx_v9_4_3_check_rlcg_range() argument 1374 gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) gfx_v9_4_3_is_rlcg_access_range() argument 1381 gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, bool enable, int xcc_id) gfx_v9_4_3_xcc_cp_compute_enable() argument 1394 gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_cp_compute_load_microcode() argument 1446 struct amdgpu_device *adev = ring->adev; gfx_v9_4_3_xcc_kiq_setting() local 1459 struct amdgpu_device *adev = ring->adev; gfx_v9_4_3_mqd_set_priority() local 1472 struct amdgpu_device *adev = ring->adev; gfx_v9_4_3_xcc_mqd_init() local 1601 struct amdgpu_device *adev = ring->adev; gfx_v9_4_3_xcc_kiq_init_register() local 1715 struct amdgpu_device *adev = ring->adev; gfx_v9_4_3_xcc_q_fini_register() local 1754 struct amdgpu_device *adev = ring->adev; gfx_v9_4_3_xcc_kiq_init_queue() local 1801 struct amdgpu_device *adev = ring->adev; gfx_v9_4_3_xcc_kcq_init_queue() local 1837 gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_kcq_fini_register() argument 1858 gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_kiq_resume() argument 1882 gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_kcq_resume() argument 1911 gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_cp_resume() argument 1947 gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) gfx_v9_4_3_cp_resume() argument 1970 gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable, int xcc_id) gfx_v9_4_3_xcc_cp_enable() argument 1976 gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_fini() argument 2013 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_4_3_hw_init() local 2033 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_4_3_hw_fini() local 2059 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_4_3_is_idle() local 2074 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_4_3_wait_for_idle() local 2088 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_4_3_soft_reset() local 2149 struct amdgpu_device *adev = ring->adev; gfx_v9_4_3_ring_emit_gds_switch() local 2174 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_4_3_early_init() local 2192 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_4_3_late_init() local 2210 gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, bool enable, int xcc_id) gfx_v9_4_3_xcc_update_sram_fgcg() argument 2232 gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, bool enable, int xcc_id) gfx_v9_4_3_xcc_update_repeater_fgcg() argument 2254 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable, int xcc_id) gfx_v9_4_3_xcc_update_medium_grain_clock_gating() argument 2319 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, bool enable, int xcc_id) gfx_v9_4_3_xcc_update_coarse_grain_clock_gating() argument 2366 gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, bool enable, int xcc_id) gfx_v9_4_3_xcc_update_gfx_clock_gating() argument 2426 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_4_3_set_clockgating_state() local 2447 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_4_3_get_clockgating_state() local 2480 struct amdgpu_device *adev = ring->adev; gfx_v9_4_3_ring_emit_hdp_flush() local 2612 struct amdgpu_device *adev = ring->adev; gfx_v9_4_3_ring_set_wptr_compute() local 2626 struct amdgpu_device *adev = ring->adev; gfx_v9_4_3_ring_emit_fence_kiq() local 2653 struct amdgpu_device *adev = ring->adev; gfx_v9_4_3_ring_emit_rreg() local 2704 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( struct amdgpu_device *adev, int me, int pipe, enum amdgpu_interrupt_state state, int xcc_id) gfx_v9_4_3_xcc_set_compute_eop_interrupt_state() argument 2757 gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) gfx_v9_4_3_set_priv_reg_fault_state() argument 2780 gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) gfx_v9_4_3_set_priv_inst_fault_state() argument 2803 gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type, enum amdgpu_interrupt_state state) gfx_v9_4_3_set_eop_interrupt_state() argument 2853 gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) gfx_v9_4_3_eop_irq() argument 2891 gfx_v9_4_3_fault(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry) gfx_v9_4_3_fault() argument 2923 gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) gfx_v9_4_3_priv_reg_irq() argument 2932 gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) gfx_v9_4_3_priv_inst_irq() argument 2963 struct amdgpu_device *adev = ring->adev; gfx_v9_4_3_emit_wave_limit_cs() local 2993 struct amdgpu_device *adev = ring->adev; gfx_v9_4_3_emit_wave_limit() local 3762 gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, void *ras_error_status, int xcc_id) gfx_v9_4_3_inst_query_ras_err_count() argument 3811 gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, void *ras_error_status, int xcc_id) gfx_v9_4_3_inst_reset_ras_err_count() argument 3844 gfx_v9_4_3_inst_query_ea_err_status(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_inst_query_ea_err_status() argument 3877 gfx_v9_4_3_inst_query_utc_err_status(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_inst_query_utc_err_status() argument 3903 gfx_v9_4_3_log_cu_timeout_status(struct amdgpu_device *adev, uint32_t status, int xcc_id) gfx_v9_4_3_log_cu_timeout_status() argument 3945 gfx_v9_4_3_inst_query_sq_timeout_status(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_inst_query_sq_timeout_status() argument 3978 gfx_v9_4_3_inst_query_ras_err_status(struct amdgpu_device *adev, void *ras_error_status, int xcc_id) gfx_v9_4_3_inst_query_ras_err_status() argument 3986 gfx_v9_4_3_inst_reset_utc_err_status(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_inst_reset_utc_err_status() argument 3994 gfx_v9_4_3_inst_reset_ea_err_status(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_inst_reset_ea_err_status() argument 4015 gfx_v9_4_3_inst_reset_sq_timeout_status(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_inst_reset_sq_timeout_status() argument 4036 gfx_v9_4_3_inst_reset_ras_err_status(struct amdgpu_device *adev, void *ras_error_status, int xcc_id) gfx_v9_4_3_inst_reset_ras_err_status() argument 4044 gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, void *ras_error_status, int xcc_id) gfx_v9_4_3_inst_enable_watchdog_timer() argument 4073 gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status) gfx_v9_4_3_query_ras_error_count() argument 4080 gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) gfx_v9_4_3_reset_ras_error_count() argument 4085 gfx_v9_4_3_query_ras_error_status(struct amdgpu_device *adev) gfx_v9_4_3_query_ras_error_status() argument 4090 gfx_v9_4_3_reset_ras_error_status(struct amdgpu_device *adev) gfx_v9_4_3_reset_ras_error_status() argument 4095 gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) gfx_v9_4_3_enable_watchdog_timer() argument 4184 gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) gfx_v9_4_3_set_ring_funcs() argument 4213 gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) gfx_v9_4_3_set_irq_funcs() argument 4225 gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) gfx_v9_4_3_set_rlc_funcs() argument 4231 gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) gfx_v9_4_3_set_gds_init() argument 4261 gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, u32 bitmap, int xcc_id) gfx_v9_4_3_set_user_cu_inactive_bitmap() argument 4275 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_get_cu_active_bitmap() argument 4290 gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info) gfx_v9_4_3_get_cu_info() argument 4363 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_4_3_xcp_resume() local 4395 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_4_3_xcp_suspend() local [all...]
H A D	amdgpu.h	115 struct amdgpu_device *adev; member 448 struct amdgpu_device *adev; global() member 1094 adev_to_drm(struct amdgpu_device *adev) adev_to_drm() argument 1434 amdgpu_acpi_init(struct amdgpu_device *adev) amdgpu_acpi_init() argument 1435 amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, u64 *tmr_size) amdgpu_acpi_get_tmr_info() argument 1440 amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, struct amdgpu_numa_info *numa_info) amdgpu_acpi_get_mem_info() argument 1446 amdgpu_acpi_fini(struct amdgpu_device *adev) amdgpu_acpi_fini() argument 1447 amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) amdgpu_acpi_should_gpu_reset() argument 1451 amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, u8 dev_state, bool drv_state) amdgpu_acpi_power_shift_control() argument 1461 amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) amdgpu_acpi_is_s0ix_active() argument 1462 amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) amdgpu_acpi_is_s3_active() argument 1468 amdgpu_dm_display_resume(struct amdgpu_device *adev) amdgpu_dm_display_resume() argument 1491 amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) amdgpu_device_has_timeouts_enabled() argument 1502 amdgpu_is_tmz(struct amdgpu_device *adev) amdgpu_is_tmz() argument [all...]
H A D	gfx_v9_0.c	891 gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) gfx_v9_0_set_kiq_pm4_funcs() argument 896 gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) gfx_v9_0_init_golden_registers() argument 996 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_test_ring() local 1026 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_test_ib() local 1081 gfx_v9_0_free_microcode(struct amdgpu_device *adev) gfx_v9_0_free_microcode() argument 1093 gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) gfx_v9_0_check_fw_write_wait() argument 1195 is_raven_kicker(struct amdgpu_device *adev) is_raven_kicker() argument 1203 check_if_enlarge_doorbell_range(struct amdgpu_device *adev) check_if_enlarge_doorbell_range() argument 1213 gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) gfx_v9_0_check_if_need_gfxoff() argument 1249 gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, char *chip_name) gfx_v9_0_init_cp_gfx_microcode() argument 1282 gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, char *chip_name) gfx_v9_0_init_rlc_microcode() argument 1327 gfx_v9_0_load_mec2_fw_bin_support(struct amdgpu_device *adev) gfx_v9_0_load_mec2_fw_bin_support() argument 1337 gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, char *chip_name) gfx_v9_0_init_cp_compute_microcode() argument 1383 gfx_v9_0_init_microcode(struct amdgpu_device *adev) gfx_v9_0_init_microcode() argument 1409 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) gfx_v9_0_get_csb_size() argument 1437 gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer) gfx_v9_0_get_csb_buffer() argument 1478 gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev) gfx_v9_0_init_always_on_cu_mask() argument 1522 gfx_v9_0_init_lbpw(struct amdgpu_device *adev) gfx_v9_0_init_lbpw() argument 1571 gfx_v9_4_init_lbpw(struct amdgpu_device *adev) gfx_v9_4_init_lbpw() argument 1620 gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_lbpw() argument 1625 gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) gfx_v9_0_cp_jump_table_num() argument 1633 gfx_v9_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) gfx_v9_0_init_rlcg_reg_access_ctrl() argument 1648 gfx_v9_0_rlc_init(struct amdgpu_device *adev) gfx_v9_0_rlc_init() argument 1675 gfx_v9_0_mec_fini(struct amdgpu_device *adev) gfx_v9_0_mec_fini() argument 1681 gfx_v9_0_mec_init(struct amdgpu_device *adev) gfx_v9_0_mec_init() argument 1742 wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) wave_read_ind() argument 1752 wave_read_regs(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t regno, uint32_t num, uint32_t *out) wave_read_regs() argument 1767 gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) gfx_v9_0_read_wave_data() argument 1788 gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) gfx_v9_0_read_wave_sgprs() argument 1797 gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst) gfx_v9_0_read_wave_vgprs() argument 1807 gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) gfx_v9_0_select_me_pipe_q() argument 1834 gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) gfx_v9_0_gpu_early_init() argument 1965 gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, int mec, int pipe, int queue) gfx_v9_0_compute_ring_init() argument 2002 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_sw_init() local 2182 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_sw_fini() local 2214 gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) gfx_v9_0_tiling_mode_table_init() argument 2219 gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance, int xcc_id) gfx_v9_0_select_se_sh() argument 2242 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) gfx_v9_0_get_rb_active_bitmap() argument 2258 gfx_v9_0_setup_rb(struct amdgpu_device *adev) gfx_v9_0_setup_rb() argument 2282 gfx_v9_0_debug_trap_config_init(struct amdgpu_device *adev, uint32_t first_vmid, uint32_t last_vmid) gfx_v9_0_debug_trap_config_init() argument 2306 gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) gfx_v9_0_init_compute_vmid() argument 2344 gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev) gfx_v9_0_init_gds_vmid() argument 2362 gfx_v9_0_init_sq_config(struct amdgpu_device *adev) gfx_v9_0_init_sq_config() argument 2378 gfx_v9_0_constants_init(struct amdgpu_device *adev) gfx_v9_0_constants_init() argument 2427 gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) gfx_v9_0_wait_for_rlc_serdes() argument 2465 gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_gui_idle_interrupt() argument 2483 gfx_v9_0_init_csb(struct amdgpu_device *adev) gfx_v9_0_init_csb() argument 2532 gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev) gfx_v9_1_init_rlc_save_restore_list() argument 2635 gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) gfx_v9_0_enable_save_restore_machine() argument 2640 pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, bool enable) pwr_10_0_gfxip_control_over_cgpg() argument 2666 gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) gfx_v9_0_init_gfx_power_gating() argument 2708 gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_sck_slow_down_on_power_up() argument 2722 gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_sck_slow_down_on_power_down() argument 2736 gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_cp_power_gating() argument 2750 gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_gfx_cg_power_gating() argument 2763 gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_gfx_pipeline_powergating() argument 2780 gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_gfx_static_mg_power_gating() argument 2793 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_enable_gfx_dynamic_mg_power_gating() argument 2806 gfx_v9_0_init_pg(struct amdgpu_device *adev) gfx_v9_0_init_pg() argument 2833 gfx_v9_0_rlc_stop(struct amdgpu_device *adev) gfx_v9_0_rlc_stop() argument 2840 gfx_v9_0_rlc_reset(struct amdgpu_device *adev) gfx_v9_0_rlc_reset() argument 2848 gfx_v9_0_rlc_start(struct amdgpu_device *adev) gfx_v9_0_rlc_start() argument 2880 gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) gfx_v9_0_rlc_load_microcode() argument 2905 gfx_v9_0_rlc_resume(struct amdgpu_device *adev) gfx_v9_0_rlc_resume() argument 2955 gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) gfx_v9_0_cp_gfx_enable() argument 2966 gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) gfx_v9_0_cp_gfx_load_microcode() argument 3023 gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) gfx_v9_0_cp_gfx_start() argument 3093 gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) gfx_v9_0_cp_gfx_resume() argument 3162 gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) gfx_v9_0_cp_compute_enable() argument 3174 gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) gfx_v9_0_cp_compute_load_microcode() argument 3220 struct amdgpu_device *adev = ring->adev; gfx_v9_0_kiq_setting() local 3233 struct amdgpu_device *adev = ring->adev; gfx_v9_0_mqd_set_priority() local 3246 struct amdgpu_device *adev = ring->adev; gfx_v9_0_mqd_init() local 3378 struct amdgpu_device *adev = ring->adev; gfx_v9_0_kiq_init_register() local 3492 struct amdgpu_device *adev = ring->adev; gfx_v9_0_kiq_fini_register() local 3531 struct amdgpu_device *adev = ring->adev; gfx_v9_0_kiq_init_queue() local 3579 struct amdgpu_device *adev = ring->adev; gfx_v9_0_kcq_init_queue() local 3615 gfx_v9_0_kiq_resume(struct amdgpu_device *adev) gfx_v9_0_kiq_resume() argument 3639 gfx_v9_0_kcq_resume(struct amdgpu_device *adev) gfx_v9_0_kcq_resume() argument 3668 gfx_v9_0_cp_resume(struct amdgpu_device *adev) gfx_v9_0_cp_resume() argument 3720 gfx_v9_0_init_tcp_config(struct amdgpu_device *adev) gfx_v9_0_init_tcp_config() argument 3738 gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) gfx_v9_0_cp_enable() argument 3748 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_hw_init() local 3773 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_hw_fini() local 3834 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_is_idle() local 3846 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_wait_for_idle() local 3860 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_soft_reset() local 3919 gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) gfx_v9_0_kiq_read_clock() argument 3993 gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) gfx_v9_0_get_gpu_clock_counter() argument 4036 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_emit_gds_switch() local 4295 gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev) gfx_v9_0_do_edc_gds_workarounds() argument 4342 gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) gfx_v9_0_do_edc_gpr_workarounds() argument 4516 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_early_init() local 4542 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_ecc_late_init() local 4576 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_late_init() local 4601 gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev) gfx_v9_0_is_rlc_enabled() argument 4613 gfx_v9_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) gfx_v9_0_set_safe_mode() argument 4630 gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) gfx_v9_0_unset_safe_mode() argument 4638 gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_update_gfx_cg_power_gating() argument 4656 gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_update_gfx_mg_power_gating() argument 4675 gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_update_medium_grain_clock_gating() argument 4750 gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_update_3d_clock_gating() argument 4805 gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_update_coarse_grain_clock_gating() argument 4857 gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, bool enable) gfx_v9_0_update_gfx_clock_gating() argument 4882 gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev, unsigned int vmid) gfx_v9_0_update_spm_vmid_internal() argument 4902 gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid) gfx_v9_0_update_spm_vmid() argument 4911 gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev, uint32_t offset, struct soc15_reg_rlcg *entries, int arr_size) gfx_v9_0_check_rlcg_range() argument 4933 gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) gfx_v9_0_is_rlcg_access_range() argument 4959 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_set_powergating_state() local 5004 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_set_clockgating_state() local 5029 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v9_0_get_clockgating_state() local 5078 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_get_wptr_gfx() local 5094 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_set_wptr_gfx() local 5108 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_emit_hdp_flush() local 5188 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_patch_ce_meta() local 5220 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_patch_de_meta() local 5371 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_set_wptr_compute() local 5385 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_emit_fence_kiq() local 5417 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_emit_ce_meta() local 5460 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_preempt_ib() local 5517 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_emit_de_meta() local 5639 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_emit_rreg() local 5687 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_emit_reg_write_reg_wait() local 5701 struct amdgpu_device *adev = ring->adev; gfx_v9_0_ring_soft_recovery() local 5711 gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, enum amdgpu_interrupt_state state) gfx_v9_0_set_gfx_eop_interrupt_state() argument 5726 gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, int me, int pipe, enum amdgpu_interrupt_state state) gfx_v9_0_set_compute_eop_interrupt_state() argument 5779 gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) gfx_v9_0_set_priv_reg_fault_state() argument 5798 gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) gfx_v9_0_set_priv_inst_fault_state() argument 5825 gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) gfx_v9_0_set_cp_ecc_error_state() argument 5856 gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned type, enum amdgpu_interrupt_state state) gfx_v9_0_set_eop_interrupt_state() argument 5895 gfx_v9_0_eop_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) gfx_v9_0_eop_irq() argument 5932 gfx_v9_0_fault(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry) gfx_v9_0_fault() argument 5959 gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) gfx_v9_0_priv_reg_irq() argument 5968 gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) gfx_v9_0_priv_inst_irq() argument 6419 gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, void *inject_if, uint32_t instance_mask) gfx_v9_0_ras_error_inject() argument 6536 gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, struct ras_err_data *err_data) gfx_v9_0_query_utc_edc_status() argument 6633 gfx_v9_0_ras_error_count(struct amdgpu_device *adev, const struct soc15_reg_entry *reg, uint32_t se_id, uint32_t inst_id, uint32_t value, uint32_t *sec_count, uint32_t *ded_count) gfx_v9_0_ras_error_count() argument 6675 gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev) gfx_v9_0_reset_ras_error_count() argument 6730 gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, void *ras_error_status) gfx_v9_0_query_ras_error_count() argument 6792 struct amdgpu_device *adev = ring->adev; gfx_v9_0_emit_wave_limit_cs() local 6822 struct amdgpu_device *adev = ring->adev; gfx_v9_0_emit_wave_limit() local 7042 gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) gfx_v9_0_set_ring_funcs() argument 7081 gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) gfx_v9_0_set_irq_funcs() argument 7096 gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) gfx_v9_0_set_rlc_funcs() argument 7114 gfx_v9_0_set_gds_init(struct amdgpu_device *adev) gfx_v9_0_set_gds_init() argument 7171 gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, u32 bitmap) gfx_v9_0_set_user_cu_inactive_bitmap() argument 7185 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) gfx_v9_0_get_cu_active_bitmap() argument 7200 gfx_v9_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info) gfx_v9_0_get_cu_info() argument [all...]
H A D	gfx_v10_0.c	3554 struct amdgpu_device *adev = kiq_ring->adev; gfx10_kiq_unmap_queues() local 3623 gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) gfx_v10_0_set_kiq_pm4_funcs() argument 3628 gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) gfx_v10_0_init_spm_golden_registers() argument 3651 gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) gfx_v10_0_init_golden_registers() argument 3768 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_test_ring() local 3806 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_test_ib() local 3878 gfx_v10_0_free_microcode(struct amdgpu_device *adev) gfx_v10_0_free_microcode() argument 3890 gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) gfx_v10_0_check_fw_write_wait() argument 3926 gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) gfx_v10_0_navi10_gfxoff_should_enable() argument 3943 gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) gfx_v10_0_check_gfxoff_flag() argument 3955 gfx_v10_0_init_microcode(struct amdgpu_device *adev) gfx_v10_0_init_microcode() argument 4040 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) gfx_v10_0_get_csb_size() argument 4070 gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer) gfx_v10_0_get_csb_buffer() argument 4118 gfx_v10_0_rlc_fini(struct amdgpu_device *adev) gfx_v10_0_rlc_fini() argument 4131 gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) gfx_v10_0_init_rlcg_reg_access_ctrl() argument 4155 gfx_v10_0_rlc_init(struct amdgpu_device *adev) gfx_v10_0_rlc_init() argument 4174 gfx_v10_0_mec_fini(struct amdgpu_device *adev) gfx_v10_0_mec_fini() argument 4180 gfx_v10_0_me_init(struct amdgpu_device *adev) gfx_v10_0_me_init() argument 4187 gfx_v10_0_mec_init(struct amdgpu_device *adev) gfx_v10_0_mec_init() argument 4249 wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) wave_read_ind() argument 4257 wave_read_regs(struct amdgpu_device *adev, uint32_t wave, uint32_t thread, uint32_t regno, uint32_t num, uint32_t *out) wave_read_regs() argument 4270 gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) gfx_v10_0_read_wave_data() argument 4298 gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) gfx_v10_0_read_wave_sgprs() argument 4309 gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst) gfx_v10_0_read_wave_vgprs() argument 4319 gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) gfx_v10_0_select_me_pipe_q() argument 4325 gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, bool enable) gfx_v10_0_update_perfmon_mgcg() argument 4352 gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) gfx_v10_0_gpu_early_init() argument 4421 gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, int me, int pipe, int queue) gfx_v10_0_gfx_ring_init() argument 4451 gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, int mec, int pipe, int queue) gfx_v10_0_compute_ring_init() argument 4487 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_sw_init() local 4639 gfx_v10_0_pfp_fini(struct amdgpu_device *adev) gfx_v10_0_pfp_fini() argument 4646 gfx_v10_0_ce_fini(struct amdgpu_device *adev) gfx_v10_0_ce_fini() argument 4653 gfx_v10_0_me_fini(struct amdgpu_device *adev) gfx_v10_0_me_fini() argument 4663 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_sw_fini() local 4691 gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance, int xcc_id) gfx_v10_0_select_se_sh() argument 4718 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) gfx_v10_0_get_rb_active_bitmap() argument 4734 gfx_v10_0_setup_rb(struct amdgpu_device *adev) gfx_v10_0_setup_rb() argument 4765 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) gfx_v10_0_init_pa_sc_tile_steering_override() argument 4806 gfx_v10_0_debug_trap_config_init(struct amdgpu_device *adev, uint32_t first_vmid, uint32_t last_vmid) gfx_v10_0_debug_trap_config_init() argument 4829 gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) gfx_v10_0_init_compute_vmid() argument 4867 gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) gfx_v10_0_init_gds_vmid() argument 4886 gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) gfx_v10_0_tcp_harvest() argument 4953 gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) gfx_v10_0_get_tcc_info() argument 4971 gfx_v10_0_constants_init(struct amdgpu_device *adev) gfx_v10_0_constants_init() argument 5008 gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) gfx_v10_0_enable_gui_idle_interrupt() argument 5030 gfx_v10_0_init_csb(struct amdgpu_device *adev) gfx_v10_0_init_csb() argument 5051 gfx_v10_0_rlc_stop(struct amdgpu_device *adev) gfx_v10_0_rlc_stop() argument 5059 gfx_v10_0_rlc_reset(struct amdgpu_device *adev) gfx_v10_0_rlc_reset() argument 5067 gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, bool enable) gfx_v10_0_rlc_smu_handshake_cntl() argument 5089 gfx_v10_0_rlc_start(struct amdgpu_device *adev) gfx_v10_0_rlc_start() argument 5102 gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) gfx_v10_0_rlc_enable_srm() argument 5113 gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) gfx_v10_0_rlc_load_microcode() argument 5141 gfx_v10_0_rlc_resume(struct amdgpu_device *adev) gfx_v10_0_rlc_resume() argument 5206 gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) gfx_v10_0_parse_rlc_toc() argument 5243 gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) gfx_v10_0_calc_toc_total_size() argument 5266 gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_buffer_init() argument 5286 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_buffer_fini() argument 5296 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, FIRMWARE_ID id, const void *fw_data, uint32_t fw_size) gfx_v10_0_rlc_backdoor_autoload_copy_ucode() argument 5323 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode() argument 5336 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode() argument 5397 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode() argument 5431 gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_enable() argument 5464 gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_config_me_cache() argument 5501 gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_config_ce_cache() argument 5538 gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache() argument 5575 gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) gfx_v10_0_rlc_backdoor_autoload_config_mec_cache() argument 5612 gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) gfx_v10_0_wait_for_rlc_autoload_complete() argument 5655 gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) gfx_v10_0_cp_gfx_enable() argument 5684 gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) gfx_v10_0_cp_gfx_load_pfp_microcode() argument 5762 gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) gfx_v10_0_cp_gfx_load_ce_microcode() argument 5839 gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) gfx_v10_0_cp_gfx_load_me_microcode() argument 5916 gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) gfx_v10_0_cp_gfx_load_microcode() argument 5946 gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) gfx_v10_0_cp_gfx_start() argument 6026 gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, CP_PIPE_ID pipe) gfx_v10_0_cp_gfx_switch_pipe() argument 6037 gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, struct amdgpu_ring *ring) gfx_v10_0_cp_gfx_set_doorbell() argument 6082 gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) gfx_v10_0_cp_gfx_resume() argument 6185 gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) gfx_v10_0_cp_compute_enable() argument 6228 gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) gfx_v10_0_cp_compute_load_microcode() argument 6301 struct amdgpu_device *adev = ring->adev; gfx_v10_0_kiq_setting() local 6331 gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, struct v10_gfx_mqd *mqd, struct amdgpu_mqd_prop *prop) gfx_v10_0_gfx_mqd_set_priority() argument 6349 gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, struct amdgpu_mqd_prop *prop) gfx_v10_0_gfx_mqd_init() argument 6434 struct amdgpu_device *adev = ring->adev; gfx_v10_0_gfx_init_queue() local 6469 gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) gfx_v10_0_cp_async_gfx_ring_resume() argument 6499 gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, struct amdgpu_mqd_prop *prop) gfx_v10_0_compute_mqd_init() argument 6616 struct amdgpu_device *adev = ring->adev; gfx_v10_0_kiq_init_register() local 6725 struct amdgpu_device *adev = ring->adev; gfx_v10_0_kiq_init_queue() local 6764 struct amdgpu_device *adev = ring->adev; gfx_v10_0_kcq_init_queue() local 6791 gfx_v10_0_kiq_resume(struct amdgpu_device *adev) gfx_v10_0_kiq_resume() argument 6815 gfx_v10_0_kcq_resume(struct amdgpu_device *adev) gfx_v10_0_kcq_resume() argument 6844 gfx_v10_0_cp_resume(struct amdgpu_device *adev) gfx_v10_0_cp_resume() argument 6901 gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) gfx_v10_0_cp_enable() argument 6907 gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) gfx_v10_0_check_grbm_cam_remapping() argument 6951 gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) gfx_v10_0_setup_grbm_cam_remapping() argument 7088 gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) gfx_v10_0_disable_gpa_mode() argument 7104 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_hw_init() local 7157 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_hw_fini() local 7197 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_is_idle() local 7210 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_wait_for_idle() local 7228 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_soft_reset() local 7306 gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) gfx_v10_0_get_gpu_clock_counter() argument 7368 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_emit_gds_switch() local 7393 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_early_init() local 7437 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_late_init() local 7451 gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) gfx_v10_0_is_rlc_enabled() argument 7460 gfx_v10_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id) gfx_v10_0_set_safe_mode() argument 7501 gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) gfx_v10_0_unset_safe_mode() argument 7523 gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable) gfx_v10_0_update_medium_grain_clock_gating() argument 7597 gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, bool enable) gfx_v10_0_update_3d_clock_gating() argument 7656 gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, bool enable) gfx_v10_0_update_coarse_grain_clock_gating() argument 7715 gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, bool enable) gfx_v10_0_update_fine_grain_clock_gating() argument 7754 gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) gfx_v10_0_apply_medium_grain_clock_gating_workaround() argument 7845 gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, bool enable) gfx_v10_0_update_gfx_clock_gating() argument 7892 gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, unsigned int vmid) gfx_v10_0_update_spm_vmid_internal() argument 7913 gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid) gfx_v10_0_update_spm_vmid() argument 7922 gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, uint32_t offset, struct soc15_reg_rlcg *entries, int arr_size) gfx_v10_0_check_rlcg_range() argument 7944 gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) gfx_v10_0_is_rlcg_access_range() argument 7949 gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) gfx_v10_cntl_power_gating() argument 7985 gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) gfx_v10_cntl_pg() argument 8026 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_set_powergating_state() local 8064 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_set_clockgating_state() local 8092 struct amdgpu_device *adev = (struct amdgpu_device *)handle; gfx_v10_0_get_clockgating_state() local 8142 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_get_wptr_gfx() local 8158 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_set_wptr_gfx() local 8221 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_set_wptr_compute() local 8263 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_emit_hdp_flush() local 8445 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_emit_fence_kiq() local 8540 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_preempt_ib() local 8586 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_emit_ce_meta() local 8626 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_emit_de_meta() local 8687 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_emit_rreg() local 8735 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_emit_reg_write_reg_wait() local 8751 struct amdgpu_device *adev = ring->adev; gfx_v10_0_ring_soft_recovery() local 8762 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, uint32_t me, uint32_t pipe, enum amdgpu_interrupt_state state) gfx_v10_0_set_gfx_eop_interrupt_state() argument 8803 gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, int me, int pipe, enum amdgpu_interrupt_state state) gfx_v10_0_set_compute_eop_interrupt_state() argument 8856 gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned int type, enum amdgpu_interrupt_state state) gfx_v10_0_set_eop_interrupt_state() argument 8898 gfx_v10_0_eop_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) gfx_v10_0_eop_irq() argument 8953 gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned int type, enum amdgpu_interrupt_state state) gfx_v10_0_set_priv_reg_fault_state() argument 8972 gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned int type, enum amdgpu_interrupt_state state) gfx_v10_0_set_priv_inst_fault_state() argument 8991 gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry) gfx_v10_0_handle_priv_fault() argument 9025 gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) gfx_v10_0_priv_reg_irq() argument 9034 gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) gfx_v10_0_priv_inst_irq() argument 9043 gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *src, unsigned int type, enum amdgpu_interrupt_state state) gfx_v10_0_kiq_set_interrupt_state() argument 9088 gfx_v10_0_kiq_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) gfx_v10_0_kiq_irq() argument 9266 gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) gfx_v10_0_set_ring_funcs() argument 9299 gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) gfx_v10_0_set_irq_funcs() argument 9314 gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) gfx_v10_0_set_rlc_funcs() argument 9339 gfx_v10_0_set_gds_init(struct amdgpu_device *adev) gfx_v10_0_set_gds_init() argument 9351 gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) gfx_v10_0_set_mqd_funcs() argument 9365 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, u32 bitmap) gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh() argument 9379 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) gfx_v10_0_get_wgp_active_bitmap_per_sh() argument 9399 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) gfx_v10_0_get_cu_active_bitmap_per_sh() argument 9417 gfx_v10_0_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info) gfx_v10_0_get_cu_info() argument 9473 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) gfx_v10_3_get_disabled_sa() argument 9493 gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) gfx_v10_3_program_pbb_mode() argument 9514 gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) gfx_v10_3_set_power_brake_sequence() argument [all...]
/kernel/linux/linux-6.6/drivers/dma/
H A D	pl330.c	3005 pl330_probe(struct amba_device *adev, const struct amba_id *id) in pl330_probe() argument 3210 pl330_remove(struct amba_device *adev) pl330_remove() argument [all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/mellanox/mlx4/
H A D	mlx4.h	885 struct mlx4_adev **adev; member
/kernel/linux/linux-6.6/drivers/pci/
H A D	pci.c	6511 struct acpi_device *adev; in pci_pr3_present() local
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/legacy-dpm/
H A D	si_dpm.c	1852 si_get_pi(struct amdgpu_device *adev) si_get_pi() argument 1885 si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev, const struct ni_leakage_coeffients *coeff, u16 v, s32 t, u32 i_leakage, u32 *leakage) si_calculate_leakage_for_v_and_t() argument 1913 si_calculate_leakage_for_v(struct amdgpu_device *adev, const struct ni_leakage_coeffients *coeff, const u32 fixed_kt, u16 v, u32 i_leakage, u32 *leakage) si_calculate_leakage_for_v() argument 1924 si_update_dte_from_pl2(struct amdgpu_device *adev, struct si_dte_data *dte_data) si_update_dte_from_pl2() argument 1954 rv770_get_pi(struct amdgpu_device *adev) rv770_get_pi() argument 1961 ni_get_pi(struct amdgpu_device *adev) ni_get_pi() argument 1975 si_initialize_powertune_defaults(struct amdgpu_device *adev) si_initialize_powertune_defaults() argument 2179 si_get_smc_power_scaling_factor(struct amdgpu_device *adev) si_get_smc_power_scaling_factor() argument 2184 si_calculate_cac_wintime(struct amdgpu_device *adev) si_calculate_cac_wintime() argument 2209 si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev, bool adjust_polarity, u32 tdp_adjustment, u32 *tdp_limit, u32 *near_tdp_limit) si_calculate_adjusted_tdp_limits() argument 2242 si_populate_smc_tdp_limits(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state) si_populate_smc_tdp_limits() argument 2307 si_populate_smc_tdp_limits_2(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state) si_populate_smc_tdp_limits_2() argument 2339 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev, const u16 prev_std_vddc, const u16 curr_std_vddc) si_calculate_power_efficiency_ratio() argument 2361 si_should_disable_uvd_powertune(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state) si_should_disable_uvd_powertune() argument 2373 evergreen_get_pi(struct amdgpu_device *adev) evergreen_get_pi() argument 2380 si_populate_power_containment_values(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SISLANDS_SMC_SWSTATE *smc_state) si_populate_power_containment_values() argument 2473 si_populate_sq_ramping_values(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SISLANDS_SMC_SWSTATE *smc_state) si_populate_sq_ramping_values() argument 2530 si_enable_power_containment(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state, bool enable) si_enable_power_containment() argument 2560 si_initialize_smc_dte_tables(struct amdgpu_device *adev) si_initialize_smc_dte_tables() argument 2627 si_get_cac_std_voltage_max_min(struct amdgpu_device *adev, u16 *max, u16 *min) si_get_cac_std_voltage_max_min() argument 2671 si_init_dte_leakage_table(struct amdgpu_device *adev, PP_SIslands_CacConfig *cac_tables, u16 vddc_max, u16 vddc_min, u16 vddc_step, u16 t0, u16 t_step) si_init_dte_leakage_table() argument 2711 si_init_simplified_leakage_table(struct amdgpu_device *adev, PP_SIslands_CacConfig *cac_tables, u16 vddc_max, u16 vddc_min, u16 vddc_step) si_init_simplified_leakage_table() argument 2746 si_initialize_smc_cac_tables(struct amdgpu_device *adev) si_initialize_smc_cac_tables() argument 2832 si_program_cac_config_registers(struct amdgpu_device *adev, const struct si_cac_config_reg *cac_config_regs) si_program_cac_config_registers() argument 2871 si_initialize_hardware_cac_manager(struct amdgpu_device *adev) si_initialize_hardware_cac_manager() argument 2894 si_enable_smc_cac(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state, bool enable) si_enable_smc_cac() argument 2941 si_init_smc_spll_table(struct amdgpu_device *adev) si_init_smc_spll_table() argument 3012 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev, u16 vce_voltage) si_get_lower_of_leakage_and_vce_voltage() argument 3030 si_get_vce_clock_voltage(struct amdgpu_device *adev, u32 evclk, u32 ecclk, u16 *voltage) si_get_vce_clock_voltage() argument 3064 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_vblank_too_short() local 3076 ni_copy_and_switch_arb_sets(struct amdgpu_device *adev, u32 arb_freq_src, u32 arb_freq_dest) ni_copy_and_switch_arb_sets() argument 3141 ni_update_current_ps(struct amdgpu_device *adev, struct amdgpu_ps *rps) ni_update_current_ps() argument 3154 ni_update_requested_ps(struct amdgpu_device *adev, struct amdgpu_ps *rps) ni_update_requested_ps() argument 3167 ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev, struct amdgpu_ps *new_ps, struct amdgpu_ps *old_ps) ni_set_uvd_clock_before_set_eng_clock() argument 3185 ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev, struct amdgpu_ps *new_ps, struct amdgpu_ps *old_ps) ni_set_uvd_clock_after_set_eng_clock() argument 3231 btc_get_valid_mclk(struct amdgpu_device *adev, u32 max_mclk, u32 requested_mclk) btc_get_valid_mclk() argument 3238 btc_get_valid_sclk(struct amdgpu_device *adev, u32 max_sclk, u32 requested_sclk) btc_get_valid_sclk() argument 3282 btc_adjust_clock_combinations(struct amdgpu_device *adev, const struct amdgpu_clock_and_voltage_limits *max_limits, struct rv7xx_pl *pl) btc_adjust_clock_combinations() argument 3309 btc_apply_voltage_delta_rules(struct amdgpu_device *adev, u16 max_vddc, u16 max_vddci, u16 *vddc, u16 *vddci) btc_apply_voltage_delta_rules() argument 3389 rv770_get_memory_module_index(struct amdgpu_device *adev) rv770_get_memory_module_index() argument 3394 rv770_get_max_vddc(struct amdgpu_device *adev) rv770_get_max_vddc() argument 3405 rv770_get_engine_memory_ss(struct amdgpu_device *adev) rv770_get_engine_memory_ss() argument 3422 si_apply_state_adjust_rules(struct amdgpu_device *adev, struct amdgpu_ps *rps) si_apply_state_adjust_rules() argument 3648 si_write_smc_soft_register(struct amdgpu_device *adev, u16 reg_offset, u32 value) si_write_smc_soft_register() argument 3658 si_is_special_1gb_platform(struct amdgpu_device *adev) si_is_special_1gb_platform() argument 3686 si_get_leakage_vddc(struct amdgpu_device *adev) si_get_leakage_vddc() argument 3705 si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev, u32 index, u16 *leakage_voltage) si_get_leakage_voltage_from_leakage_index() argument 3732 si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources) si_set_dpm_event_sources() argument 3767 si_enable_auto_throttle_source(struct amdgpu_device *adev, enum si_dpm_auto_throttle_src source, bool enable) si_enable_auto_throttle_source() argument 3786 si_start_dpm(struct amdgpu_device *adev) si_start_dpm() argument 3791 si_stop_dpm(struct amdgpu_device *adev) si_stop_dpm() argument 3796 si_enable_sclk_control(struct amdgpu_device *adev, bool enable) si_enable_sclk_control() argument 3838 si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, PPSMC_Msg msg, u32 parameter) si_send_msg_to_smc_with_parameter() argument 3845 si_restrict_performance_levels_before_switch(struct amdgpu_device *adev) si_restrict_performance_levels_before_switch() argument 3857 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_force_performance_level() local 3895 si_set_sw_state(struct amdgpu_device *adev) si_set_sw_state() argument 3901 si_halt_smc(struct amdgpu_device *adev) si_halt_smc() argument 3910 si_resume_smc(struct amdgpu_device *adev) si_resume_smc() argument 3919 si_dpm_start_smc(struct amdgpu_device *adev) si_dpm_start_smc() argument 3926 si_dpm_stop_smc(struct amdgpu_device *adev) si_dpm_stop_smc() argument 3932 si_process_firmware_header(struct amdgpu_device *adev) si_process_firmware_header() argument 4022 si_read_clock_registers(struct amdgpu_device *adev) si_read_clock_registers() argument 4043 si_enable_thermal_protection(struct amdgpu_device *adev, bool enable) si_enable_thermal_protection() argument 4052 si_enable_acpi_power_management(struct amdgpu_device *adev) si_enable_acpi_power_management() argument 4085 si_notify_smc_display_change(struct amdgpu_device *adev, bool has_display) si_notify_smc_display_change() argument 4095 si_program_response_times(struct amdgpu_device *adev) si_program_response_times() argument 4123 si_program_ds_registers(struct amdgpu_device *adev) si_program_ds_registers() argument 4141 si_program_display_gap(struct amdgpu_device *adev) si_program_display_gap() argument 4186 si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable) si_enable_spread_spectrum() argument 4199 si_setup_bsp(struct amdgpu_device *adev) si_setup_bsp() argument 4223 si_program_git(struct amdgpu_device *adev) si_program_git() argument 4228 si_program_tp(struct amdgpu_device *adev) si_program_tp() argument 4248 si_program_tpp(struct amdgpu_device *adev) si_program_tpp() argument 4253 si_program_sstp(struct amdgpu_device *adev) si_program_sstp() argument 4258 si_enable_display_gap(struct amdgpu_device *adev) si_enable_display_gap() argument 4272 si_program_vc(struct amdgpu_device *adev) si_program_vc() argument 4279 si_clear_vc(struct amdgpu_device *adev) si_clear_vc() argument 4319 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk) si_get_strobe_mode_settings() argument 4339 si_upload_firmware(struct amdgpu_device *adev) si_upload_firmware() argument 4349 si_validate_phase_shedding_tables(struct amdgpu_device *adev, const struct atom_voltage_table *table, const struct amdgpu_phase_shedding_limits_table *limits) si_validate_phase_shedding_tables() argument 4376 si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev, u32 max_voltage_steps, struct atom_voltage_table *voltage_table) si_trim_voltage_table_to_fit_state_table() argument 4393 si_get_svi2_voltage_table(struct amdgpu_device *adev, struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table, struct atom_voltage_table *voltage_table) si_get_svi2_voltage_table() argument 4414 si_construct_voltage_tables(struct amdgpu_device *adev) si_construct_voltage_tables() argument 4494 si_populate_smc_voltage_table(struct amdgpu_device *adev, const struct atom_voltage_table *voltage_table, SISLANDS_SMC_STATETABLE *table) si_populate_smc_voltage_table() argument 4504 si_populate_smc_voltage_tables(struct amdgpu_device *adev, SISLANDS_SMC_STATETABLE *table) si_populate_smc_voltage_tables() argument 4567 si_populate_voltage_value(struct amdgpu_device *adev, const struct atom_voltage_table *table, u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) si_populate_voltage_value() argument 4587 si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk, SISLANDS_SMC_VOLTAGE_VALUE *voltage) si_populate_mvdd_value() argument 4604 si_get_std_voltage_value(struct amdgpu_device *adev, SISLANDS_SMC_VOLTAGE_VALUE *voltage, u16 *std_voltage) si_get_std_voltage_value() argument 4655 si_populate_std_voltage_value(struct amdgpu_device *adev, u16 value, u8 index, SISLANDS_SMC_VOLTAGE_VALUE *voltage) si_populate_std_voltage_value() argument 4665 si_populate_phase_shedding_value(struct amdgpu_device *adev, const struct amdgpu_phase_shedding_limits_table *limits, u16 voltage, u32 sclk, u32 mclk, SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) si_populate_phase_shedding_value() argument 4684 si_init_arb_table_index(struct amdgpu_device *adev) si_init_arb_table_index() argument 4702 si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev) si_initial_switch_from_arb_f0_to_f1() argument 4707 si_reset_to_default(struct amdgpu_device *adev) si_reset_to_default() argument 4713 si_force_switch_to_arb_f0(struct amdgpu_device *adev) si_force_switch_to_arb_f0() argument 4732 si_calculate_memory_refresh_rate(struct amdgpu_device *adev, u32 engine_clock) si_calculate_memory_refresh_rate() argument 4751 si_populate_memory_timing_parameters(struct amdgpu_device *adev, struct rv7xx_pl *pl, SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) si_populate_memory_timing_parameters() argument 4777 si_do_program_memory_timing_parameters(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, unsigned int first_arb_set) si_do_program_memory_timing_parameters() argument 4804 si_program_memory_timing_parameters(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state) si_program_memory_timing_parameters() argument 4811 si_populate_initial_mvdd_value(struct amdgpu_device *adev, struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) si_populate_initial_mvdd_value() argument 4824 si_populate_smc_initial_state(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_initial_state, SISLANDS_SMC_STATETABLE *table) si_populate_smc_initial_state() argument 4945 si_gen_pcie_gen_support(struct amdgpu_device *adev, u32 sys_mask, enum si_pcie_gen asic_gen, enum si_pcie_gen default_gen) si_gen_pcie_gen_support() argument 4970 si_populate_smc_acpi_state(struct amdgpu_device *adev, SISLANDS_SMC_STATETABLE *table) si_populate_smc_acpi_state() argument 5112 si_populate_ulv_state(struct amdgpu_device *adev, struct SISLANDS_SMC_SWSTATE_SINGLE *state) si_populate_ulv_state() argument 5143 si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev) si_program_ulv_memory_timing_parameters() argument 5169 si_get_mvdd_configuration(struct amdgpu_device *adev) si_get_mvdd_configuration() argument 5176 si_init_smc_table(struct amdgpu_device *adev) si_init_smc_table() argument 5265 si_calculate_sclk_params(struct amdgpu_device *adev, u32 engine_clock, SISLANDS_SMC_SCLK_VALUE *sclk) si_calculate_sclk_params() argument 5335 si_populate_sclk_value(struct amdgpu_device *adev, u32 engine_clock, SISLANDS_SMC_SCLK_VALUE *sclk) si_populate_sclk_value() argument 5356 si_populate_mclk_value(struct amdgpu_device *adev, u32 engine_clock, u32 memory_clock, SISLANDS_SMC_MCLK_VALUE *mclk, bool strobe_mode, bool dll_state_on) si_populate_mclk_value() argument 5445 si_populate_smc_sp(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SISLANDS_SMC_SWSTATE *smc_state) si_populate_smc_sp() argument 5460 si_convert_power_level_to_smc(struct amdgpu_device *adev, struct rv7xx_pl *pl, SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) si_convert_power_level_to_smc() argument 5569 si_populate_smc_t(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SISLANDS_SMC_SWSTATE *smc_state) si_populate_smc_t() argument 5618 si_disable_ulv(struct amdgpu_device *adev) si_disable_ulv() argument 5630 si_is_state_ulv_compatible(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state) si_is_state_ulv_compatible() argument 5658 si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state) si_set_power_state_conditionally_enable_ulv() argument 5672 si_convert_power_state_to_smc(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SISLANDS_SMC_SWSTATE *smc_state) si_convert_power_state_to_smc() argument 5752 si_upload_sw_state(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state) si_upload_sw_state() argument 5773 si_upload_ulv_state(struct amdgpu_device *adev) si_upload_ulv_state() argument 5796 si_upload_smc_data(struct amdgpu_device *adev) si_upload_smc_data() argument 5835 si_set_mc_special_registers(struct amdgpu_device *adev, struct si_mc_reg_table *table) si_set_mc_special_registers() argument 6006 si_initialize_mc_reg_table(struct amdgpu_device *adev) si_initialize_mc_reg_table() argument 6056 si_populate_mc_reg_addresses(struct amdgpu_device *adev, SMC_SIslands_MCRegisters *mc_reg_table) si_populate_mc_reg_addresses() argument 6090 si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev, struct rv7xx_pl *pl, SMC_SIslands_MCRegisterSet *mc_reg_table_data) si_convert_mc_reg_table_entry_to_smc() argument 6110 si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state, SMC_SIslands_MCRegisters *mc_reg_table) si_convert_mc_reg_table_to_smc() argument 6124 si_populate_mc_reg_table(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_boot_state) si_populate_mc_reg_table() argument 6162 si_upload_mc_reg_table(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state) si_upload_mc_reg_table() argument 6182 si_enable_voltage_control(struct amdgpu_device *adev, bool enable) si_enable_voltage_control() argument 6190 si_get_maximum_link_speed(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_state) si_get_maximum_link_speed() argument 6205 si_get_current_pcie_speed(struct amdgpu_device *adev) si_get_current_pcie_speed() argument 6215 si_request_link_speed_change_before_state_change(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state, struct amdgpu_ps *amdgpu_current_state) si_request_link_speed_change_before_state_change() argument 6255 si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state, struct amdgpu_ps *amdgpu_current_state) si_notify_link_speed_change_after_state_change() argument 6300 si_set_max_cu_value(struct amdgpu_device *adev) si_set_max_cu_value() argument 6341 si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev, struct amdgpu_clock_voltage_dependency_table *table) si_patch_single_dependency_table_based_on_leakage() argument 6372 si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev) si_patch_dependency_tables_based_on_leakage() argument 6391 si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev, struct amdgpu_ps *amdgpu_new_state, struct amdgpu_ps *amdgpu_current_state) si_set_pcie_lane_width_in_smc() argument 6408 si_dpm_setup_asic(struct amdgpu_device *adev) si_dpm_setup_asic() argument 6414 si_thermal_enable_alert(struct amdgpu_device *adev, bool enable) si_thermal_enable_alert() argument 6437 si_thermal_set_temperature_range(struct amdgpu_device *adev, int min_temp, int max_temp) si_thermal_set_temperature_range() argument 6462 si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode) si_fan_ctrl_set_static_mode() argument 6484 si_thermal_setup_fan_table(struct amdgpu_device *adev) si_thermal_setup_fan_table() argument 6553 si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev) si_fan_ctrl_start_smc_fan_control() argument 6567 si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev) si_fan_ctrl_stop_smc_fan_control() argument 6587 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_get_fan_speed_pwm() local 6611 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_set_fan_speed_pwm() local 6644 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_set_fan_control_mode() local 6667 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_get_fan_control_mode() local 6735 si_fan_ctrl_set_default_mode(struct amdgpu_device *adev) si_fan_ctrl_set_default_mode() argument 6752 si_thermal_start_smc_fan_control(struct amdgpu_device *adev) si_thermal_start_smc_fan_control() argument 6760 si_thermal_initialize(struct amdgpu_device *adev) si_thermal_initialize() argument 6775 si_thermal_start_thermal_controller(struct amdgpu_device *adev) si_thermal_start_thermal_controller() argument 6802 si_thermal_stop_thermal_controller(struct amdgpu_device *adev) si_thermal_stop_thermal_controller() argument 6810 si_dpm_enable(struct amdgpu_device *adev) si_dpm_enable() argument 6928 si_set_temperature_range(struct amdgpu_device *adev) si_set_temperature_range() argument 6945 si_dpm_disable(struct amdgpu_device *adev) si_dpm_disable() argument 6971 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_pre_set_power_state() local 6982 si_power_control_set_level(struct amdgpu_device *adev) si_power_control_set_level() argument 7005 si_set_vce_clock(struct amdgpu_device *adev, struct amdgpu_ps *new_rps, struct amdgpu_ps *old_rps) si_set_vce_clock() argument 7025 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_set_power_state() local 7129 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_post_set_power_state() local 7147 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_display_configuration_changed() local 7153 si_parse_pplib_non_clock_info(struct amdgpu_device *adev, struct amdgpu_ps *rps, struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, u8 table_rev) si_parse_pplib_non_clock_info() argument 7179 si_parse_pplib_clock_info(struct amdgpu_device *adev, struct amdgpu_ps *rps, int index, union pplib_clock_info *clock_info) si_parse_pplib_clock_info() argument 7260 si_parse_power_table(struct amdgpu_device *adev) si_parse_power_table() argument 7350 si_dpm_init(struct amdgpu_device *adev) si_dpm_init() argument 7513 si_dpm_fini(struct amdgpu_device *adev) si_dpm_fini() argument 7529 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_debugfs_print_current_performance_level() local 7548 si_dpm_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, enum amdgpu_interrupt_state state) si_dpm_set_interrupt_state() argument 7596 si_dpm_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) si_dpm_process_interrupt() argument 7629 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_late_init() local 7652 si_dpm_init_microcode(struct amdgpu_device *adev) si_dpm_init_microcode() argument 7728 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_sw_init() local 7774 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_sw_fini() local 7787 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_hw_init() local 7804 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_hw_fini() local 7814 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_suspend() local 7828 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_resume() local 7878 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_get_temp() local 7895 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_get_sclk() local 7907 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_get_mclk() local 7920 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_print_power_state() local 7944 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_early_init() local 7972 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_check_state_equal() local 8009 struct amdgpu_device *adev = (struct amdgpu_device *)handle; si_dpm_read_sensor() local 8100 si_dpm_set_irq_funcs(struct amdgpu_device *adev) si_dpm_set_irq_funcs() argument [all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/inc/
H A D	hwmgr.h	744 void *adev; member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/swsmu/inc/
H A D	amdgpu_smu.h	471 struct amdgpu_device *adev; member

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Indexes created Thu Nov 07 10:32:03 CST 2024