Lines Matching defs:adev
114 struct amdgpu_device *adev;
297 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
299 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
301 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
330 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
335 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
338 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
344 bool amdgpu_get_bios(struct amdgpu_device *adev);
345 bool amdgpu_read_bios(struct amdgpu_device *adev);
425 struct amdgpu_device *adev;
468 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
472 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
477 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
478 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
479 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
497 struct amdgpu_device *adev;
554 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
555 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
560 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
566 void amdgpu_test_moves(struct amdgpu_device *adev);
588 bool (*read_disabled_bios)(struct amdgpu_device *adev);
589 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
591 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
593 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
594 int (*reset)(struct amdgpu_device *adev);
595 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
597 u32 (*get_xclk)(struct amdgpu_device *adev);
599 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
600 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
602 int (*get_pcie_lanes)(struct amdgpu_device *adev);
603 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
605 u32 (*get_config_memsize)(struct amdgpu_device *adev);
607 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
609 void (*invalidate_hdp)(struct amdgpu_device *adev,
611 void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev);
613 bool (*need_full_reset)(struct amdgpu_device *adev);
615 void (*init_doorbell_index)(struct amdgpu_device *adev);
617 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
620 bool (*need_reset_on_init)(struct amdgpu_device *adev);
622 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
624 bool (*supports_baco)(struct amdgpu_device *adev);
626 void (*pre_asic_init)(struct amdgpu_device *adev);
666 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1007 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1009 return &adev->ddev;
1017 int amdgpu_device_init(struct amdgpu_device *adev,
1019 void amdgpu_device_fini(struct amdgpu_device *adev);
1020 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1022 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1024 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1026 void amdgpu_device_wreg(struct amdgpu_device *adev,
1029 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1031 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1032 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1034 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1035 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1037 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1040 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1043 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1046 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1051 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1053 int emu_soc_asic_init(struct amdgpu_device *adev);
1060 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1061 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1063 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1064 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1066 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1067 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1069 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1070 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1071 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1074 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1075 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1076 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1077 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1078 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1079 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1080 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1081 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1082 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1083 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1084 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1085 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1086 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1087 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1088 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1089 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1090 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1091 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1117 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1118 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1119 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1140 #define RBIOS8(i) (adev->bios[i])
1147 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1148 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1149 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1150 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1151 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1152 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1153 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1154 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1155 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1156 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1157 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1158 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1159 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1160 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1161 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
1162 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1163 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1164 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1165 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1166 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1167 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1168 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1170 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1173 bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1174 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1175 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1177 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1178 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1180 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1182 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1183 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1189 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1223 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1229 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1259 int amdgpu_acpi_init(struct amdgpu_device *adev);
1260 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1261 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1262 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1264 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1266 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1269 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1270 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1278 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1280 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1284 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1285 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1311 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1313 return adev->gmc.tmz_enabled;
1316 static inline int amdgpu_in_reset(struct amdgpu_device *adev)
1318 return atomic_read(&adev->in_gpu_reset);