Lines Matching defs:adev
115 struct amdgpu_device *adev;
337 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
339 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
341 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
370 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
375 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
378 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
384 bool amdgpu_get_bios(struct amdgpu_device *adev);
385 bool amdgpu_read_bios(struct amdgpu_device *adev);
386 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
448 struct amdgpu_device *adev;
491 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
492 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
497 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
541 bool (*read_disabled_bios)(struct amdgpu_device *adev);
542 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
544 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
546 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
547 int (*reset)(struct amdgpu_device *adev);
548 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
550 u32 (*get_xclk)(struct amdgpu_device *adev);
552 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
553 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
555 int (*get_pcie_lanes)(struct amdgpu_device *adev);
556 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
558 u32 (*get_config_memsize)(struct amdgpu_device *adev);
560 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
562 void (*invalidate_hdp)(struct amdgpu_device *adev,
565 bool (*need_full_reset)(struct amdgpu_device *adev);
567 void (*init_doorbell_index)(struct amdgpu_device *adev);
569 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
572 bool (*need_reset_on_init)(struct amdgpu_device *adev);
574 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
576 bool (*supports_baco)(struct amdgpu_device *adev);
578 void (*pre_asic_init)(struct amdgpu_device *adev);
580 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
582 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
611 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
684 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev,
687 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev,
754 int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
1094 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1096 return &adev->ddev;
1104 int amdgpu_device_init(struct amdgpu_device *adev,
1106 void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1107 void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1109 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1111 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1113 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1116 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1118 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
1121 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1123 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
1125 void amdgpu_device_wreg(struct amdgpu_device *adev,
1128 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
1130 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1132 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1133 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1135 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1137 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1139 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1141 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1143 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);
1145 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1147 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
1149 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1155 int emu_soc_asic_init(struct amdgpu_device *adev);
1163 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1164 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1166 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1167 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1169 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1170 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1172 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1173 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1174 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1177 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1178 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1179 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1180 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1181 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))
1182 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
1183 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1184 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1185 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1186 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1187 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1188 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1189 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1190 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1191 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1192 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1193 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1194 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1195 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1196 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1222 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1243 #define RBIOS8(i) (adev->bios[i])
1250 #define amdgpu_asic_set_vga_state(adev, state) \
1251 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0)
1252 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1253 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1254 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1255 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1256 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1257 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1258 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1259 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1260 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1261 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1262 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1263 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1264 #define amdgpu_asic_flush_hdp(adev, r) \
1265 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1266 #define amdgpu_asic_invalidate_hdp(adev, r) \
1267 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1268 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0))
1269 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1270 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1271 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1272 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1273 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1274 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1275 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1276 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1277 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1278 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1280 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1290 bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1291 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1292 int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1295 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1296 int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1297 bool amdgpu_device_need_post(struct amdgpu_device *adev);
1299 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1302 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1304 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1305 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1309 int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1315 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1320 void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1322 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1325 void amdgpu_device_halt(struct amdgpu_device *adev);
1326 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1328 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1330 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
1332 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
1363 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1371 int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1414 int amdgpu_acpi_init(struct amdgpu_device *adev);
1415 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1416 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1418 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1420 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1423 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1424 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
1426 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
1430 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1434 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1435 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev,
1440 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev,
1446 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1447 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
1451 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1458 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1459 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1461 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1462 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1466 int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1468 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1472 void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1473 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1484 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1486 int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1488 int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1491 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1494 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1495 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1496 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1497 adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1502 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1504 return adev->gmc.tmz_enabled;
1507 int amdgpu_in_reset(struct amdgpu_device *adev);