| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.cc | 3340 SimVRegister& zdn = ReadVRegister(instr->GetRd()); in Simulator() local
3348 eor(vform, zdn, temp, zdn); in Simulator()
3351 not_(vform, temp, zdn); in Simulator()
3352 bsl(vform, zdn, zk, temp, zm); in Simulator()
3356 bsl(vform, zdn, zk, zdn, temp); in Simulator()
3359 bsl(vform, zdn, zk, zdn, zm); in Simulator()
3362 eor(vform, temp, zdn, z in Simulator()
3377 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
3415 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
3455 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
3485 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
3513 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
3548 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
3563 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
9738 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
9787 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
9868 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
10189 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
10250 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
10433 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
10939 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
11102 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
11126 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
11153 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
11178 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
11227 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
13135 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
13280 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
13332 SimVRegister& zdn = ReadVRegister(instr->GetRd()); Simulator() local
[all...] |
| H A D | assembler-sve-aarch64.cc | 86 void Assembler::SVELogicalImmediate(const ZRegister& zdn, in SVELogicalImmediate() argument
90 unsigned lane_size = zdn.GetLaneSizeInBits(); in SVELogicalImmediate()
93 Emit(op | Rd(zdn) | SVEBitN(bit_n) | SVEImmRotate(imm_r, lane_size) | in SVELogicalImmediate()
168 void Assembler::SVEBitwiseShiftImmediatePred(const ZRegister& zdn, in SVEBitwiseShiftImmediatePred() argument
175 Emit(op | tszh | tszl_and_imm | PgLow8(pg) | Rd(zdn)); in SVEBitwiseShiftImmediatePred()
539 void Assembler::FN(const ZRegister& zdn, int pattern, int multiplier) { \
541 VIXL_ASSERT(zdn.GetLaneSizeInBytes() == k##T##RegSizeInBytes); \
542 Emit(OP##T##_z_zs | Rd(zdn) | ImmSVEPredicateConstraint(pattern) | \
1403 void Assembler::fmad(const ZRegister& zdn, in fmad() argument
1412 VIXL_ASSERT(AreSameLaneSize(zdn, z in fmad()
1448 fmsb(const ZRegister& zdn, const PRegisterM& pg, const ZRegister& zm, const ZRegister& za) fmsb() argument
1463 fnmad(const ZRegister& zdn, const PRegisterM& pg, const ZRegister& zm, const ZRegister& za) fnmad() argument
1508 fnmsb(const ZRegister& zdn, const PRegisterM& pg, const ZRegister& zm, const ZRegister& za) fnmsb() argument
2034 decp(const ZRegister& zdn, const PRegister& pg) decp() argument
2059 incp(const ZRegister& zdn, const PRegister& pg) incp() argument
2099 sqdecp(const ZRegister& zdn, const PRegister& pg) sqdecp() argument
2138 sqincp(const ZRegister& zdn, const PRegister& pg) sqincp() argument
2163 uqdecp(const ZRegister& zdn, const PRegister& pg) uqdecp() argument
2187 uqincp(const ZRegister& zdn, const PRegister& pg) uqincp() argument
3173 mad(const ZRegister& zdn, const PRegisterM& pg, const ZRegister& zm, const ZRegister& za) mad() argument
3215 msb(const ZRegister& zdn, const PRegisterM& pg, const ZRegister& zm, const ZRegister& za) msb() argument
5990 insr(const ZRegister& zdn, const Register& rm) insr() argument
6000 insr(const ZRegister& zdn, const VRegister& vm) insr() argument
[all...] |
| H A D | macro-assembler-aarch64.h | 4185 void Decd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) { in Decd() argument
4188 decd(zdn, pattern, multiplier); in Decd()
4195 void Dech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) { in Dech() argument
4198 dech(zdn, pattern, multiplier); in Dech()
4212 void Decp(const ZRegister& zdn, const PRegister& pg) { Decp(zdn, pg, zdn); } in Decp() argument
4218 void Decw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) { in Decw() argument
4221 decw(zdn, pattern, multiplier); in Decw()
4557 void Fmad(const ZRegister& zdn, in Fmad() argument
4689 Fmsb(const ZRegister& zdn, const PRegisterM& pg, const ZRegister& zm, const ZRegister& za) Fmsb() argument
4910 Incd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Incd() argument
4920 Inch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Inch() argument
4937 Incp(const ZRegister& zdn, const PRegister& pg) Incp() argument
4943 Incw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Incw() argument
4949 Insr(const ZRegister& zdn, const Register& rm) Insr() argument
4954 Insr(const ZRegister& zdn, const VRegister& vm) Insr() argument
5893 Sqdecd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Sqdecd() argument
5911 Sqdech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Sqdech() argument
5935 Sqdecp(const ZRegister& zdn, const PRegister& pg) Sqdecp() argument
5951 Sqdecw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Sqdecw() argument
5982 Sqincd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Sqincd() argument
6000 Sqinch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Sqinch() argument
6024 Sqincp(const ZRegister& zdn, const PRegister& pg) Sqincp() argument
6040 Sqincw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Sqincw() argument
6318 Uqdecd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Uqdecd() argument
6328 Uqdech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Uqdech() argument
6359 Uqdecp(const ZRegister& zdn, const PRegister& pg) Uqdecp() argument
6367 Uqdecw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Uqdecw() argument
6382 Uqincd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Uqincd() argument
6392 Uqinch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Uqinch() argument
6423 Uqincp(const ZRegister& zdn, const PRegister& pg) Uqincp() argument
6431 Uqincw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) Uqincw() argument
[all...] |
| H A D | assembler-aarch64.h | 4025 void decd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
4031 void dech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
4037 void decp(const ZRegister& zdn, const PRegister& pg);
4043 void decw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
4275 void fmad(const ZRegister& zdn,
4376 void fmsb(const ZRegister& zdn,
4413 void fnmad(const ZRegister& zdn,
4434 void fnmsb(const ZRegister& zdn,
4530 void incd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
4536 void inch(const ZRegister& zdn, in
[all...] |
| H A D | macro-assembler-sve-aarch64.cc | 944 void MacroAssembler::Insr(const ZRegister& zdn, IntegerOperand imm) { in Insr() argument
946 VIXL_ASSERT(imm.FitsInLane(zdn)); in Insr()
950 insr(zdn, xzr); in Insr()
955 Register scratch = temps.AcquireRegisterToHoldLane(zdn); in Insr()
963 insr(zdn, scratch); in Insr()
977 // zdn = za + (zdn * zm) in Mla()
1004 // zdn = za - (zdn * zm) in Mls()
1679 // zdn in SVEDotIndexHelper()
[all...] |
| /third_party/vixl/test/aarch64/ |
| H A D | test-utils-aarch64.h | 661 const ZRegister& zdn, in InsrHelper()
664 masm->Insr(zdn, values[i]); in InsrHelper()
660 InsrHelper(MacroAssembler* masm, const ZRegister& zdn, const T (&values)[N]) InsrHelper() argument
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