Lines Matching refs:zdn
4185 void Decd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
4188 decd(zdn, pattern, multiplier);
4195 void Dech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
4198 dech(zdn, pattern, multiplier);
4212 void Decp(const ZRegister& zdn, const PRegister& pg) { Decp(zdn, pg, zdn); }
4218 void Decw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
4221 decw(zdn, pattern, multiplier);
4557 void Fmad(const ZRegister& zdn,
4563 fmad(zdn, pg, zm, za);
4689 void Fmsb(const ZRegister& zdn,
4695 fmsb(zdn, pg, zm, za);
4910 void Incd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
4913 incd(zdn, pattern, multiplier);
4920 void Inch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
4923 inch(zdn, pattern, multiplier);
4937 void Incp(const ZRegister& zdn, const PRegister& pg) { Incp(zdn, pg, zdn); }
4943 void Incw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
4946 incw(zdn, pattern, multiplier);
4949 void Insr(const ZRegister& zdn, const Register& rm) {
4952 insr(zdn, rm);
4954 void Insr(const ZRegister& zdn, const VRegister& vm) {
4957 insr(zdn, vm);
4959 void Insr(const ZRegister& zdn, IntegerOperand imm);
5893 void Sqdecd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
5896 sqdecd(zdn, pattern, multiplier);
5911 void Sqdech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
5914 sqdech(zdn, pattern, multiplier);
5935 void Sqdecp(const ZRegister& zdn, const PRegister& pg) {
5936 Sqdecp(zdn, pg, zdn);
5951 void Sqdecw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
5954 sqdecw(zdn, pattern, multiplier);
5982 void Sqincd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
5985 sqincd(zdn, pattern, multiplier);
6000 void Sqinch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
6003 sqinch(zdn, pattern, multiplier);
6024 void Sqincp(const ZRegister& zdn, const PRegister& pg) {
6025 Sqincp(zdn, pg, zdn);
6040 void Sqincw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
6043 sqincw(zdn, pattern, multiplier);
6318 void Uqdecd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
6321 uqdecd(zdn, pattern, multiplier);
6328 void Uqdech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
6331 uqdech(zdn, pattern, multiplier);
6359 void Uqdecp(const ZRegister& zdn, const PRegister& pg) {
6360 Uqdecp(zdn, pg, zdn);
6367 void Uqdecw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
6370 uqdecw(zdn, pattern, multiplier);
6382 void Uqincd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
6385 uqincd(zdn, pattern, multiplier);
6392 void Uqinch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
6395 uqinch(zdn, pattern, multiplier);
6423 void Uqincp(const ZRegister& zdn, const PRegister& pg) {
6424 Uqincp(zdn, pg, zdn);
6431 void Uqincw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
6434 uqincw(zdn, pattern, multiplier);
8490 typedef void (Assembler::*SVEMulAddPredicatedZdnFn)(const ZRegister& zdn,