Lines Matching refs:zdn

86 void Assembler::SVELogicalImmediate(const ZRegister& zdn,
90 unsigned lane_size = zdn.GetLaneSizeInBits();
93 Emit(op | Rd(zdn) | SVEBitN(bit_n) | SVEImmRotate(imm_r, lane_size) |
168 void Assembler::SVEBitwiseShiftImmediatePred(const ZRegister& zdn,
175 Emit(op | tszh | tszl_and_imm | PgLow8(pg) | Rd(zdn));
539 void Assembler::FN(const ZRegister& zdn, int pattern, int multiplier) { \
541 VIXL_ASSERT(zdn.GetLaneSizeInBytes() == k##T##RegSizeInBytes); \
542 Emit(OP##T##_z_zs | Rd(zdn) | ImmSVEPredicateConstraint(pattern) | \
1403 void Assembler::fmad(const ZRegister& zdn,
1412 VIXL_ASSERT(AreSameLaneSize(zdn, zm, za));
1413 VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1415 Emit(FMAD_z_p_zzz | SVESize(zdn) | Rd(zdn) | PgLow8(pg) | Rn(zm) | Rm(za));
1448 void Assembler::fmsb(const ZRegister& zdn,
1457 VIXL_ASSERT(AreSameLaneSize(zdn, zm, za));
1458 VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1460 Emit(FMSB_z_p_zzz | SVESize(zdn) | Rd(zdn) | PgLow8(pg) | Rn(zm) | Rm(za));
1463 void Assembler::fnmad(const ZRegister& zdn,
1472 VIXL_ASSERT(AreSameLaneSize(zdn, zm, za));
1473 VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1475 Emit(FNMAD_z_p_zzz | SVESize(zdn) | Rd(zdn) | PgLow8(pg) | Rn(zm) | Rm(za));
1508 void Assembler::fnmsb(const ZRegister& zdn,
1517 VIXL_ASSERT(AreSameLaneSize(zdn, zm, za));
1518 VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
1520 Emit(FNMSB_z_p_zzz | SVESize(zdn) | Rd(zdn) | PgLow8(pg) | Rn(zm) | Rm(za));
2034 void Assembler::decp(const ZRegister& zdn, const PRegister& pg) {
2041 VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
2044 Emit(DECP_z_p_z | SVESize(zdn) | Rd(zdn) | Pg<8, 5>(pg));
2059 void Assembler::incp(const ZRegister& zdn, const PRegister& pg) {
2066 VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
2069 Emit(INCP_z_p_z | SVESize(zdn) | Rd(zdn) | Pg<8, 5>(pg));
2099 void Assembler::sqdecp(const ZRegister& zdn, const PRegister& pg) {
2105 VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
2108 Emit(SQDECP_z_p_z | SVESize(zdn) | Rd(zdn) | Pg<8, 5>(pg));
2138 void Assembler::sqincp(const ZRegister& zdn, const PRegister& pg) {
2144 VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
2147 Emit(SQINCP_z_p_z | SVESize(zdn) | Rd(zdn) | Pg<8, 5>(pg));
2163 void Assembler::uqdecp(const ZRegister& zdn, const PRegister& pg) {
2169 VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
2172 Emit(UQDECP_z_p_z | SVESize(zdn) | Rd(zdn) | Pg<8, 5>(pg));
2187 void Assembler::uqincp(const ZRegister& zdn, const PRegister& pg) {
2193 VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
2196 Emit(UQINCP_z_p_z | SVESize(zdn) | Rd(zdn) | Pg<8, 5>(pg));
3173 void Assembler::mad(const ZRegister& zdn,
3182 VIXL_ASSERT(AreSameLaneSize(zdn, zm, za));
3184 Emit(MAD_z_p_zzz | SVESize(zdn) | Rd(zdn) | PgLow8(pg) | Rm(zm) | Rn(za));
3215 void Assembler::msb(const ZRegister& zdn,
3224 VIXL_ASSERT(AreSameLaneSize(zdn, zm, za));
3226 Emit(MSB_z_p_zzz | SVESize(zdn) | Rd(zdn) | PgLow8(pg) | Rm(zm) | Rn(za));
5990 void Assembler::insr(const ZRegister& zdn, const Register& rm) {
5997 Emit(INSR_z_r | SVESize(zdn) | Rd(zdn) | Rn(rm));
6000 void Assembler::insr(const ZRegister& zdn, const VRegister& vm) {
6008 Emit(INSR_z_v | SVESize(zdn) | Rd(zdn) | Rn(vm));