/third_party/mesa3d/src/gallium/drivers/virgl/ |
H A D | virgl_transfer_queue.c | 179 queue->num_dwords -= (VIRGL_TRANSFER3D_SIZE + 1); in replace_unmapped_transfer() 246 if (queue->num_dwords + dwords >= VIRGL_MAX_TBUF_DWORDS) { in add_internal() 256 queue->num_dwords = 0; in add_internal() 261 queue->num_dwords += dwords; in add_internal() 271 queue->num_dwords = 0; in virgl_transfer_queue_init() 298 queue->num_dwords = 0; in virgl_transfer_queue_fini() 343 queue->num_dwords = 0; in virgl_transfer_queue_clear()
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H A D | virgl_transfer_queue.h | 40 uint32_t num_dwords; member
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H A D | virgl_context.c | 964 ctx->queue.num_dwords == 0 && in virgl_flush_eq()
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/third_party/mesa3d/src/gallium/drivers/iris/ |
H A D | iris_genx_macros.h | 111 #define iris_emit_merge(batch, dwords0, dwords1, num_dwords) \ 113 uint32_t *dw = __gen_get_batch_dwords(batch, num_dwords); \ 114 for (uint32_t i = 0; i < num_dwords; i++) \ 116 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
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H A D | iris_state.c | 5725 const uint32_t num_dwords = 2 + 2 * n; in emit_push_constant_packet_all() local 5731 all.DWordLength = num_dwords - 2; in emit_push_constant_packet_all() 5745 iris_batch_emit(batch, const_all, sizeof(uint32_t) * num_dwords); in emit_push_constant_packet_all()
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/third_party/mesa3d/src/gallium/drivers/crocus/ |
H A D | crocus_genx_macros.h | 116 #define crocus_emit_merge(batch, dwords0, dwords1, num_dwords) \ 118 uint32_t *dw = __gen_get_batch_dwords(batch, num_dwords); \ 119 for (uint32_t i = 0; i < num_dwords; i++) \ 121 VG(VALGRIND_CHECK_MEM_IS_DEFINED(dw, num_dwords)); \
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/third_party/mesa3d/src/imagination/vulkan/ |
H A D | pvr_csb.c | 208 * \param[in] num_dwords Number of dwords to allocate. 211 void *pvr_csb_alloc_dwords(struct pvr_csb *csb, uint32_t num_dwords) in pvr_csb_alloc_dwords() argument 213 const uint32_t required_space = num_dwords * 4; in pvr_csb_alloc_dwords()
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H A D | pvr_csb.h | 125 void *pvr_csb_alloc_dwords(struct pvr_csb *csb, uint32_t num_dwords);
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/third_party/mesa3d/src/gallium/drivers/radeonsi/ |
H A D | si_test_dma_perf.c | 202 unsigned num_dwords = size / 4; in si_test_dma_perf() local 203 unsigned num_instructions = DIV_ROUND_UP(num_dwords, dwords_per_instruction); in si_test_dma_perf() 209 info.grid[0] = DIV_ROUND_UP(num_dwords, dwords_per_wave); in si_test_dma_perf()
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H A D | si_compute_blit.c | 281 unsigned num_dwords = size / 4; in si_compute_clear_buffer_rmw() local 282 unsigned num_instructions = DIV_ROUND_UP(num_dwords, dwords_per_instruction); in si_compute_clear_buffer_rmw() 288 info.grid[0] = DIV_ROUND_UP(num_dwords, dwords_per_wave); in si_compute_clear_buffer_rmw() 367 unsigned num_dwords = size / 4; in si_compute_do_clear_or_copy() local 368 unsigned num_instructions = DIV_ROUND_UP(num_dwords, dwords_per_instruction); in si_compute_do_clear_or_copy() 374 info.grid[0] = DIV_ROUND_UP(num_dwords, dwords_per_wave); in si_compute_do_clear_or_copy()
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H A D | si_sqtt.c | 776 const void *data, uint32_t num_dwords) in si_emit_thread_trace_userdata() 782 while (num_dwords > 0) { in si_emit_thread_trace_userdata() 783 uint32_t count = MIN2(num_dwords, 2); in si_emit_thread_trace_userdata() 792 num_dwords -= count; in si_emit_thread_trace_userdata() 774 si_emit_thread_trace_userdata(struct si_context* sctx, struct radeon_cmdbuf *cs, const void *data, uint32_t num_dwords) si_emit_thread_trace_userdata() argument
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H A D | si_descriptors.c | 1894 unsigned num_dwords) in si_upload_bindless_descriptor() 1904 si_cp_write_data(sctx, desc->buffer, va - desc->buffer->gpu_address, num_dwords * 4, V_370_TC_L2, in si_upload_bindless_descriptor() 1893 si_upload_bindless_descriptor(struct si_context *sctx, unsigned desc_slot, unsigned num_dwords) si_upload_bindless_descriptor() argument
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/third_party/mesa3d/src/amd/vulkan/ |
H A D | radv_sqtt.c | 339 uint32_t num_dwords) in radv_emit_thread_trace_userdata() 349 while (num_dwords > 0) { in radv_emit_thread_trace_userdata() 350 uint32_t count = MIN2(num_dwords, 2); in radv_emit_thread_trace_userdata() 363 num_dwords -= count; in radv_emit_thread_trace_userdata() 338 radv_emit_thread_trace_userdata(struct radv_cmd_buffer *cmd_buffer, const void *data, uint32_t num_dwords) radv_emit_thread_trace_userdata() argument
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H A D | radv_private.h | 2963 uint32_t num_dwords);
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/third_party/mesa3d/src/amd/common/ |
H A D | sid.h | 216 #define EOP_DATA_GDS(dw_offset, num_dwords) ((dw_offset) | ((unsigned)(num_dwords) << 16))
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/third_party/mesa3d/src/intel/common/tests/ |
H A D | mi_builder_test.cpp | 48 void * __gen_get_batch_dwords(mi_builder_test *test, unsigned num_dwords); 91 void *emit_dwords(int num_dwords); 291 mi_builder_test::emit_dwords(int num_dwords) 294 batch_offset += num_dwords * 4; 377 __gen_get_batch_dwords(mi_builder_test *test, unsigned num_dwords) 379 return test->emit_dwords(num_dwords);
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/third_party/mesa3d/src/intel/common/ |
H A D | mi_builder.h | 45 * unsigned num_dwords); 689 unsigned num_dwords) in _mi_builder_push_math() 691 assert(num_dwords < MI_BUILDER_MAX_MATH_DWORDS); in _mi_builder_push_math() 692 if (b->num_math_dwords + num_dwords > MI_BUILDER_MAX_MATH_DWORDS) in _mi_builder_push_math() 696 dwords, num_dwords * sizeof(*dwords)); in _mi_builder_push_math() 697 b->num_math_dwords += num_dwords; in _mi_builder_push_math() 687 _mi_builder_push_math(struct mi_builder *b, const uint32_t *dwords, unsigned num_dwords) _mi_builder_push_math() argument
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/third_party/mesa3d/src/intel/vulkan/ |
H A D | gfx7_cmd_buffer.c | 293 uint32_t num_dwords = GENX(BLEND_STATE_length) + in cmd_buffer_flush_dynamic_state() local 298 pipeline->gfx7.blend_state, num_dwords, 64); in cmd_buffer_flush_dynamic_state()
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H A D | gfx8_cmd_buffer.c | 691 uint32_t num_dwords = GENX(BLEND_STATE_length) + in cmd_buffer_flush_dynamic_state() local 696 pipeline->gfx8.blend_state, num_dwords, 64); in cmd_buffer_flush_dynamic_state()
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H A D | anv_batch_chain.c | 280 anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords) in anv_batch_emit_dwords() argument 282 if (batch->next + num_dwords * 4 > batch->end) { in anv_batch_emit_dwords() 292 batch->next += num_dwords * 4; in anv_batch_emit_dwords()
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H A D | genX_cmd_buffer.c | 1070 const unsigned num_dwords = GFX_VER >= 10 ? in init_fast_clear_color() local 1073 for (unsigned i = 0; i < num_dwords; i++) { in init_fast_clear_color() 3289 const uint32_t num_dwords = 2 + 2 * buffer_count; in cmd_buffer_emit_push_constant_all() local 3291 dw = anv_batch_emitn(&cmd_buffer->batch, num_dwords, in cmd_buffer_emit_push_constant_all() 3821 const uint32_t num_dwords = 1 + num_buffers * 4; in cmd_buffer_flush_state() local 3823 p = anv_batch_emitn(&cmd_buffer->batch, num_dwords, in cmd_buffer_flush_state()
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H A D | genX_pipeline.c | 116 const uint32_t num_dwords = 1 + total_elems * 2; in emit_vertex_input() local 117 p = anv_batch_emitn(&pipeline->base.batch, num_dwords, in emit_vertex_input()
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H A D | anv_private.h | 1552 void *anv_batch_emit_dwords(struct anv_batch *batch, int num_dwords);
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/third_party/mesa3d/src/intel/compiler/ |
H A D | brw_eu.h | 820 unsigned num_dwords, in brw_dp_oword_block_rw_desc() 832 SET_BITS(BRW_DATAPORT_OWORD_BLOCK_DWORDS(num_dwords), 2, 0); in brw_dp_oword_block_rw_desc() 865 unsigned num_dwords, in brw_dp_a64_oword_block_rw_desc() 877 SET_BITS(BRW_DATAPORT_OWORD_BLOCK_DWORDS(num_dwords), 2, 0); in brw_dp_a64_oword_block_rw_desc() 818 brw_dp_oword_block_rw_desc(const struct intel_device_info *devinfo, bool align_16B, unsigned num_dwords, bool write) brw_dp_oword_block_rw_desc() argument 863 brw_dp_a64_oword_block_rw_desc(const struct intel_device_info *devinfo, bool align_16B, unsigned num_dwords, bool write) brw_dp_a64_oword_block_rw_desc() argument
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/third_party/mesa3d/src/intel/blorp/ |
H A D | blorp_genX_exec.h | 422 const unsigned num_dwords = 1 + num_vbs * GENX(VERTEX_BUFFER_STATE_length); in blorp_emit_vertex_buffers() local 423 uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_BUFFERS), num_dwords); in blorp_emit_vertex_buffers() 571 const unsigned num_dwords = in blorp_emit_vertex_elements() local 573 uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_ELEMENTS), num_dwords); in blorp_emit_vertex_elements() 1919 const unsigned num_dwords = GENX(MI_ATOMIC_length) + inlinedata_dw; in blorp_update_clear_color() local 1922 uint32_t *dw = blorp_emitn(batch, GENX(MI_ATOMIC), num_dwords, in blorp_update_clear_color() 1934 dw = blorp_emitn(batch, GENX(MI_ATOMIC), num_dwords, in blorp_update_clear_color()
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