Home
last modified time | relevance | path

Searched refs:imm5 (Results 1 - 17 of 17) sorted by relevance

/third_party/node/deps/v8/src/codegen/mips64/
H A Dassembler-mips64.h877 void addvi_b(MSARegister wd, MSARegister ws, uint32_t imm5);
878 void addvi_h(MSARegister wd, MSARegister ws, uint32_t imm5);
879 void addvi_w(MSARegister wd, MSARegister ws, uint32_t imm5);
880 void addvi_d(MSARegister wd, MSARegister ws, uint32_t imm5);
881 void subvi_b(MSARegister wd, MSARegister ws, uint32_t imm5);
882 void subvi_h(MSARegister wd, MSARegister ws, uint32_t imm5);
883 void subvi_w(MSARegister wd, MSARegister ws, uint32_t imm5);
884 void subvi_d(MSARegister wd, MSARegister ws, uint32_t imm5);
885 void maxi_s_b(MSARegister wd, MSARegister ws, uint32_t imm5);
886 void maxi_s_h(MSARegister wd, MSARegister ws, uint32_t imm5);
[all...]
H A Dassembler-mips64.cc1199 int32_t imm5, MSARegister ws, MSARegister wd) { in GenInstrMsaI5()
1205 ? is_int5(imm5) in GenInstrMsaI5()
1206 : is_uint5(imm5)); in GenInstrMsaI5()
1207 Instr instr = MSA | operation | df | ((imm5 & kImm5Mask) << kWtShift) | in GenInstrMsaI5()
3237 uint32_t imm5) { \
3238 GenInstrMsaI5(opcode, I5_DF_##format, imm5, ws, wd); \
1198 GenInstrMsaI5(SecondaryField operation, SecondaryField df, int32_t imm5, MSARegister ws, MSARegister wd) GenInstrMsaI5() argument
/third_party/node/deps/v8/src/codegen/mips/
H A Dassembler-mips.h817 void addvi_b(MSARegister wd, MSARegister ws, uint32_t imm5);
818 void addvi_h(MSARegister wd, MSARegister ws, uint32_t imm5);
819 void addvi_w(MSARegister wd, MSARegister ws, uint32_t imm5);
820 void addvi_d(MSARegister wd, MSARegister ws, uint32_t imm5);
821 void subvi_b(MSARegister wd, MSARegister ws, uint32_t imm5);
822 void subvi_h(MSARegister wd, MSARegister ws, uint32_t imm5);
823 void subvi_w(MSARegister wd, MSARegister ws, uint32_t imm5);
824 void subvi_d(MSARegister wd, MSARegister ws, uint32_t imm5);
825 void maxi_s_b(MSARegister wd, MSARegister ws, uint32_t imm5);
826 void maxi_s_h(MSARegister wd, MSARegister ws, uint32_t imm5);
[all...]
H A Dassembler-mips.cc1270 int32_t imm5, MSARegister ws, MSARegister wd) { in GenInstrMsaI5()
1276 ? is_int5(imm5) in GenInstrMsaI5()
1277 : is_uint5(imm5)); in GenInstrMsaI5()
1278 Instr instr = MSA | operation | df | ((imm5 & kImm5Mask) << kWtShift) | in GenInstrMsaI5()
3030 uint32_t imm5) { \
3031 GenInstrMsaI5(opcode, I5_DF_##format, imm5, ws, wd); \
1269 GenInstrMsaI5(SecondaryField operation, SecondaryField df, int32_t imm5, MSARegister ws, MSARegister wd) GenInstrMsaI5() argument
/third_party/vixl/src/aarch64/
H A Dassembler-sve-aarch64.cc2228 void Assembler::index(const ZRegister& zd, const Register& rn, int imm5) { in index() argument
2231 // size<23:22> | imm5<20:16> | Rn<9:5> | Zd<4:0> in index()
2237 Emit(INDEX_z_ri | SVESize(zd) | Rd(zd) | Rn(rn) | ImmField<20, 16>(imm5)); in index()
2240 void Assembler::index(const ZRegister& zd, int imm5, const Register& rm) { in index() argument
2243 // size<23:22> | Rm<20:16> | imm5<9:5> | Zd<4:0> in index()
2249 Emit(INDEX_z_ir | SVESize(zd) | Rd(zd) | ImmField<9, 5>(imm5) | Rm(rm)); in index()
2815 int imm5) { in cmpeq()
2818 // size<23:22> | imm5<20:16> | op<15> = 1 | o2<13> = 0 | Pg<12:10> | Zn<9:5> in cmpeq()
2824 CompareVectors(pd, pg, zn, imm5, CMPEQ_p_p_zi); in cmpeq()
2830 int imm5) { in cmpge()
2812 cmpeq(const PRegisterWithLaneSize& pd, const PRegisterZ& pg, const ZRegister& zn, int imm5) cmpeq() argument
2827 cmpge(const PRegisterWithLaneSize& pd, const PRegisterZ& pg, const ZRegister& zn, int imm5) cmpge() argument
2842 cmpgt(const PRegisterWithLaneSize& pd, const PRegisterZ& pg, const ZRegister& zn, int imm5) cmpgt() argument
2857 cmple(const PRegisterWithLaneSize& pd, const PRegisterZ& pg, const ZRegister& zn, int imm5) cmple() argument
2872 cmplt(const PRegisterWithLaneSize& pd, const PRegisterZ& pg, const ZRegister& zn, int imm5) cmplt() argument
2887 cmpne(const PRegisterWithLaneSize& pd, const PRegisterZ& pg, const ZRegister& zn, int imm5) cmpne() argument
4268 ldff1b(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) ldff1b() argument
4301 ldff1d(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) ldff1d() argument
4337 ldff1h(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) ldff1h() argument
4371 ldff1sb(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) ldff1sb() argument
4408 ldff1sh(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) ldff1sh() argument
4442 ldff1sw(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) ldff1sw() argument
4479 ldff1w(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) ldff1w() argument
4525 int64_t imm5 = addr.GetImmediateOffset(); SVEGatherPrefetchVectorPlusImmediateHelper() local
[all...]
H A Dmacro-assembler-aarch64.h3919 int imm5; in Cmpeq() local
3920 if (imm.TryEncodeAsIntNForLane<5>(zn, &imm5)) { in Cmpeq()
3922 cmpeq(pd, pg, zn, imm5); in Cmpeq()
3940 int imm5; in Cmpge() local
3941 if (imm.TryEncodeAsIntNForLane<5>(zn, &imm5)) { in Cmpge()
3943 cmpge(pd, pg, zn, imm5); in Cmpge()
3961 int imm5; in Cmpgt() local
3962 if (imm.TryEncodeAsIntNForLane<5>(zn, &imm5)) { in Cmpgt()
3964 cmpgt(pd, pg, zn, imm5); in Cmpgt()
4021 int imm5; in Cmple() local
4080 int imm5; Cmplt() local
4101 int imm5; Cmpne() local
5232 Ldff1b(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) Ldff1b() argument
5248 Ldff1d(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) Ldff1d() argument
5264 Ldff1h(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) Ldff1h() argument
5280 Ldff1sb(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) Ldff1sb() argument
5296 Ldff1sh(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) Ldff1sh() argument
5312 Ldff1sw(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) Ldff1sw() argument
5328 Ldff1w(const ZRegister& zt, const PRegisterZ& pg, const ZRegister& zn, int imm5) Ldff1w() argument
[all...]
H A Dassembler-aarch64.h3867 int imm5);
3879 int imm5);
3891 int imm5);
3927 int imm5);
3963 int imm5);
3975 int imm5);
4558 void index(const ZRegister& zd, const Register& rn, int imm5);
4562 void index(const ZRegister& zd, int imm5, const Register& rm);
4825 int imm5);
4837 int imm5);
[all...]
H A Dsimulator-aarch64.cc8174 int imm5 = instr->GetImmNEON5(); in Simulator() local
8175 int tz = CountTrailingZeros(imm5, 32); in Simulator()
8176 int reg_index = ExtractSignedBitfield32(31, tz + 1, imm5); in Simulator()
9240 int imm5 = instr->GetImmNEON5(); in Simulator() local
9241 int tz = CountTrailingZeros(imm5, 32); in Simulator()
9242 int rn_index = ExtractSignedBitfield32(31, tz + 1, imm5); in Simulator()
H A Ddisasm-aarch64.cc6820 unsigned imm5 = instr->GetImmNEON5(); in Disassembler() local
6822 int tz = CountTrailingZeros(imm5, 32); in Disassembler()
6824 rd_index = imm5 >> (tz + 1); in Disassembler()
/third_party/node/deps/v8/src/codegen/riscv64/
H A Dassembler-riscv64.cc1219 void Assembler::GenInstrV(uint8_t funct6, VRegister vd, int8_t imm5, in GenInstrV() argument
1221 DCHECK(is_uint5(imm5) || is_int5(imm5)); in GenInstrV()
1224 (((uint32_t)imm5 << kRvvImm5Shift) & kRvvImm5Mask) | in GenInstrV()
1322 ControlStatusReg csr, uint8_t imm5) { in GenInstrCSR_ii()
1323 GenInstrI(funct3, SYSTEM, rd, ToRegister(imm5), csr); in GenInstrCSR_ii()
1719 void Assembler::csrrwi(Register rd, ControlStatusReg csr, uint8_t imm5) { in csrrwi() argument
1720 GenInstrCSR_ii(0b101, rd, csr, imm5); in csrrwi()
1723 void Assembler::csrrsi(Register rd, ControlStatusReg csr, uint8_t imm5) { in csrrsi() argument
1724 GenInstrCSR_ii(0b110, rd, csr, imm5); in csrrsi()
1321 GenInstrCSR_ii(uint8_t funct3, Register rd, ControlStatusReg csr, uint8_t imm5) GenInstrCSR_ii() argument
1727 csrrci(Register rd, ControlStatusReg csr, uint8_t imm5) csrrci() argument
2524 vmerge_vi(VRegister vd, uint8_t imm5, VRegister vs2) vmerge_vi() argument
2536 vadc_vi(VRegister vd, uint8_t imm5, VRegister vs2) vadc_vi() argument
2548 vmadc_vi(VRegister vd, uint8_t imm5, VRegister vs2) vmadc_vi() argument
2559 vrgather_vi(VRegister vd, VRegister vs2, int8_t imm5, MaskType mask) vrgather_vi() argument
[all...]
H A Dassembler-riscv64.h470 void csrrwi(Register rd, ControlStatusReg csr, uint8_t imm5);
471 void csrrsi(Register rd, ControlStatusReg csr, uint8_t imm5);
472 void csrrci(Register rd, ControlStatusReg csr, uint8_t imm5);
721 void vmerge_vi(VRegister vd, uint8_t imm5, VRegister vs2);
734 void vadc_vi(VRegister vd, uint8_t imm5, VRegister vs2);
738 void vmadc_vi(VRegister vd, uint8_t imm5, VRegister vs2);
757 void name##_vi(VRegister vd, VRegister vs2, int8_t imm5, \
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.cc4797 int imm5 = instr->ImmNEON5();
4798 int lsb = LowestSetBitPosition(imm5);
4799 int reg_index = imm5 >> lsb;
5681 int imm5 = instr->ImmNEON5();
5682 int lsb = LowestSetBitPosition(imm5);
5683 int rn_index = imm5 >> lsb;
/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.h2334 int imm5 = (index << (s + 1)) | (1 << s);
2335 return imm5 << ImmNEON5_offset;
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DIceAssemblerARM32.cpp335 IOffsetT imm5) {
337 assert(imm5 < (1 << kShiftImmBits));
338 return (imm5 << kShiftImmShift) | (encodeShift(Shift) << kShiftShift) | Rm;
1701 // xxx{s}<c> <Rd>, <Rm>, #imm5
1704 // iiiii=imm5, and mmmm=Rm.
/third_party/skia/src/core/
H A DSkVM.cpp2354 void Assembler::sli4s(V d, V n, int imm5) {
2355 this->op(0b0'1'1'011110'0100'000'01010'1, n, d, ( imm5 & 5_mask)<<16);
2357 void Assembler::shl4s(V d, V n, int imm5) {
2358 this->op(0b0'1'0'011110'0100'000'01010'1, n, d, ( imm5 & 5_mask)<<16);
2360 void Assembler::sshr4s(V d, V n, int imm5) {
2361 this->op(0b0'1'0'011110'0100'000'00'0'0'0'1, n, d, (-imm5 & 5_mask)<<16);
2363 void Assembler::ushr4s(V d, V n, int imm5) {
2364 this->op(0b0'1'1'011110'0100'000'00'0'0'0'1, n, d, (-imm5 & 5_mask)<<16);
2476 int imm5 = (lane << 3) | 0b100;
2477 this->op(0b0'0'0'01110000'00000'0'01'1'1'1, src, dst, (imm5
[all...]
/third_party/node/deps/v8/src/codegen/arm/
H A Dassembler-arm.cc1905 // Rd(15-12) | imm5(11-7) | 0(6) | 01(5-4) | Rm(3-0) in pkhbt()
1920 // Rd(15-12) | imm5(11-7) | 1(6) | 01(5-4) | Rm(3-0) in pkhtb()
2247 // 1111(15-12) | imm5(11-07) | type(6-5) | 0(4)| Rm(3-0) | in pld()
3121 int imm5 = 32 - fraction_bits; in vcvt_f64_s32() local
3122 int i = imm5 & 1; in vcvt_f64_s32()
3123 int imm4 = (imm5 >> 1) & 0xF; in vcvt_f64_s32()
/third_party/ffmpeg/libavcodec/
H A DMakefile436 OBJS-$(CONFIG_IMM5_DECODER) += imm5.o

Completed in 107 milliseconds