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Searched refs:MPU_RASR_SRD_Pos (Results 1 - 7 of 7) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/m-profile/
H A Darmv7m_mpu.h105 (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_sc000.h608 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ macro
609 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
H A Dcore_cm0plus.h592 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ macro
593 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
H A Dcore_cm4.h1283 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ macro
1284 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
H A Dcore_sc300.h1201 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ macro
1202 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
H A Dcore_cm3.h1218 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ macro
1219 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
H A Dcore_cm7.h1502 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ macro
1503 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */

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