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Searched refs:MPU_RASR_SIZE_Pos (Results 1 - 7 of 7) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/m-profile/
H A Darmv7m_mpu.h106 (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_sc000.h611 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ macro
612 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
H A Dcore_cm0plus.h595 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ macro
596 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
H A Dcore_cm4.h1286 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ macro
1287 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
H A Dcore_sc300.h1204 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ macro
1205 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
H A Dcore_cm3.h1221 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ macro
1222 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
H A Dcore_cm7.h1505 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ macro
1506 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */

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