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Searched refs:MPU_RASR_ENABLE_Pos (Results 1 - 6 of 6) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_sc000.h614 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ macro
615 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
H A Dcore_cm0plus.h598 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ macro
599 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
H A Dcore_cm4.h1289 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ macro
1290 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
H A Dcore_sc300.h1207 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ macro
1208 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
H A Dcore_cm3.h1224 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ macro
1225 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
H A Dcore_cm7.h1508 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ macro
1509 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */

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