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Searched refs:ICIMVAU (Results 1 - 7 of 7) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/m-profile/
H A Darmv7m_cachel1.h123 SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ in SCB_InvalidateICache_by_Addr()
/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_starmc1.h572 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ member
3161 SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ in SCB_InvalidateICache_by_Addr()
H A Dcore_cm35p.h560 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ member
H A Dcore_cm33.h560 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ member
H A Dcore_cm7.h504 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ member
H A Dcore_cm85.h592 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ member
H A Dcore_cm55.h571 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ member

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