Searched refs:FIFO0 (Results 1 - 4 of 4) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
H A D	core_cm4.h	1062 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ member 1108 /** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */ 1109 #define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */ 1110 #define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */ 1112 #define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */ 1113 #define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */ 1115 #define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */ 1116 #define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */ 1118 #define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */ 1119 #define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0 [all...]
H A D	core_sc300.h	980 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ member 1026 /** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */ 1027 #define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */ 1028 #define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */ 1030 #define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */ 1031 #define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */ 1033 #define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */ 1034 #define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */ 1036 #define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */ 1037 #define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0 [all...]
H A D	core_cm3.h	997 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ member 1043 /** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */ 1044 #define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */ 1045 #define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */ 1047 #define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */ 1048 #define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */ 1050 #define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */ 1051 #define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */ 1053 #define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */ 1054 #define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0 [all...]
H A D	core_cm7.h	1281 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ member 1327 /** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */ 1328 #define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */ 1329 #define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */ 1331 #define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */ 1332 #define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */ 1334 #define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */ 1335 #define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */ 1337 #define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */ 1338 #define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0 [all...]

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Indexes created Thu Nov 07 10:32:03 CST 2024