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Searched refs:DCCSW (Results 1 - 7 of 7) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/m-profile/
H A Darmv7m_cachel1.h299 SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | in SCB_CleanDCache()
/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_starmc1.h577 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ member
958 #define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */
959 #define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */
961 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
962 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
964 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
965 #define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
3307 SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | in SCB_CleanDCache()
H A Dcore_cm35p.h565 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ member
931 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
932 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
934 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
935 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
H A Dcore_cm33.h565 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ member
931 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
932 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
934 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
935 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
H A Dcore_cm7.h509 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ member
837 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
838 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
840 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
841 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
H A Dcore_cm85.h597 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ member
1013 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
1014 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
1016 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
1017 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
H A Dcore_cm55.h576 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ member
992 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
993 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
995 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
996 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */

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