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Searched refs:CSSELR (Results 1 - 7 of 7) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/m-profile/
H A Darmv7m_cachel1.h148 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_EnableDCache()
192 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_DisableDCache()
254 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_InvalidateDCache()
289 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanDCache()
324 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanInvalidateDCache()
/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_starmc1.h557 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
937 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
938 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
940 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
941 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
3186 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_EnableDCache()
3224 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_DisableDCache()
3262 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_InvalidateDCache()
3297 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanDCache()
3332 SCB->CSSELR in SCB_CleanInvalidateDCache()
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H A Dcore_cm35p.h545 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
913 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
914 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
916 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
917 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
H A Dcore_cm33.h545 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
913 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
914 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
916 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
917 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
H A Dcore_cm7.h493 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
819 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
820 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
822 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
823 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
H A Dcore_cm85.h576 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
985 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
986 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
988 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
989 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
H A Dcore_cm55.h555 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
964 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
965 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
967 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
968 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */

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