Searched refs:CCSIDR (Results 1 - 7 of 7) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/m-profile/
H A D	armv7m_cachel1.h	151 ccsidr = SCB->CCSIDR; in SCB_EnableDCache() 223 locals.ccsidr = SCB->CCSIDR; in SCB_DisableDCache() 257 ccsidr = SCB->CCSIDR; in SCB_InvalidateDCache() 292 ccsidr = SCB->CCSIDR; in SCB_CleanDCache() 327 ccsidr = SCB->CCSIDR; in SCB_CleanInvalidateDCache()
/third_party/cmsis/CMSIS/Core/Include/
H A D	core_starmc1.h	556 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ member 915 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ 916 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ 918 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ 919 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ 921 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ 922 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ 924 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ 925 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ 927 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR [all...]
H A D	core_cm35p.h	544 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ member 891 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ 892 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ 894 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ 895 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ 897 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ 898 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ 900 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ 901 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ 903 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR [all...]
H A D	core_cm33.h	544 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ member 891 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ 892 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ 894 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ 895 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ 897 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ 898 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ 900 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ 901 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ 903 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR [all...]
H A D	core_cm7.h	492 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ member 797 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ 798 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ 800 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ 801 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ 803 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ 804 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ 806 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ 807 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ 809 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR [all...]
H A D	core_cm85.h	575 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ member 963 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ 964 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ 966 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ 967 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ 969 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ 970 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ 972 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ 973 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ 975 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR [all...]
H A D	core_cm55.h	554 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ member 942 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ 943 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ 945 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ 946 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ 948 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ 949 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ 951 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ 952 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ 954 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR [all...]

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Indexes created Thu Nov 07 10:32:03 CST 2024