video_div_table (reference) in projects: kernel - OpenGrok search results

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Searched refs:video_div_table (Results 1 - 10 of 10) sorted by relevance

/kernel/linux/linux-5.10/drivers/clk/imx/
H A D	clk-imx6sll.c	`66 static const struct clk_div_table video_div_table[] = { variable 182 CLK_SET_RATE_PARENT \| CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); in imx6sll_clocks_init()`
H A D	clk-imx6sl.c	`86 static const struct clk_div_table video_div_table[] = { variable 269 hws[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); in imx6sl_clocks_init()`
H A D	clk-imx6ul.c	`89 static const struct clk_div_table video_div_table[] = { variable 224 CLK_SET_RATE_PARENT \| CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); in imx6ul_clocks_init()`
H A D	clk-imx6q.c	`110 static struct clk_div_table video_div_table[] = { variable 464 video_div_table[1].div = 1; in imx6q_clocks_init() 465 video_div_table[3].div = 1; in imx6q_clocks_init() 599 hws[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); in imx6q_clocks_init()`
H A D	clk-imx6sx.c	`103 static const struct clk_div_table video_div_table[] = { variable 254 CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); in imx6sx_clocks_init()`
/kernel/linux/linux-6.6/drivers/clk/imx/
H A D	clk-imx6sll.c	`66 static const struct clk_div_table video_div_table[] = { variable 182 CLK_SET_RATE_PARENT \| CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); in imx6sll_clocks_init()`
H A D	clk-imx6sl.c	`87 static const struct clk_div_table video_div_table[] = { variable 270 hws[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); in imx6sl_clocks_init()`
H A D	clk-imx6q.c	`111 static struct clk_div_table video_div_table[] = { variable 469 video_div_table[1].div = 1; in imx6q_clocks_init() 470 video_div_table[3].div = 1; in imx6q_clocks_init() 604 hws[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); in imx6q_clocks_init()`
H A D	clk-imx6sx.c	`103 static const struct clk_div_table video_div_table[] = { variable 254 CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); in imx6sx_clocks_init()`
H A D	clk-imx6ul.c	`90 static const struct clk_div_table video_div_table[] = { variable 239 CLK_SET_RATE_PARENT \| CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); in imx6ul_clocks_init()`

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