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Searched refs:vdsc_cfg (Results 1 - 13 of 13) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/
H A Ddrm_dsc.c253 * @vdsc_cfg:
256 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) in drm_dsc_compute_rc_parameters() argument
266 if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { in drm_dsc_compute_rc_parameters()
268 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2, in drm_dsc_compute_rc_parameters()
272 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * in drm_dsc_compute_rc_parameters()
273 vdsc_cfg->bits_per_pixel, in drm_dsc_compute_rc_parameters()
277 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, in drm_dsc_compute_rc_parameters()
281 vdsc_cfg in drm_dsc_compute_rc_parameters()
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/kernel/linux/linux-6.6/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c277 * @vdsc_cfg:
280 void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg) in drm_dsc_set_const_params() argument
282 if (!vdsc_cfg->rc_model_size) in drm_dsc_set_const_params()
283 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; in drm_dsc_set_const_params()
284 vdsc_cfg->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST; in drm_dsc_set_const_params()
285 vdsc_cfg->rc_tgt_offset_high = DSC_RC_TGT_OFFSET_HI_CONST; in drm_dsc_set_const_params()
286 vdsc_cfg->rc_tgt_offset_low = DSC_RC_TGT_OFFSET_LO_CONST; in drm_dsc_set_const_params()
288 if (vdsc_cfg->bits_per_component <= 10) in drm_dsc_set_const_params()
289 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; in drm_dsc_set_const_params()
291 vdsc_cfg in drm_dsc_set_const_params()
307 drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg) drm_dsc_set_rc_buf_thresh() argument
1242 drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_type type) drm_dsc_setup_rc_params() argument
1311 drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) drm_dsc_compute_rc_parameters() argument
1445 drm_dsc_get_bpp_int(const struct drm_dsc_config *vdsc_cfg) drm_dsc_get_bpp_int() argument
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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_vdsc.c56 intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf, in intel_vdsc_set_min_max_qp() argument
59 int bpc = vdsc_cfg->bits_per_component; in intel_vdsc_set_min_max_qp()
62 vdsc_cfg->rc_range_params[buf].range_min_qp = in intel_vdsc_set_min_max_qp()
63 intel_lookup_range_min_qp(bpc, buf, bpp, vdsc_cfg->native_420); in intel_vdsc_set_min_max_qp()
64 vdsc_cfg->rc_range_params[buf].range_max_qp = in intel_vdsc_set_min_max_qp()
65 intel_lookup_range_max_qp(bpc, buf, bpp, vdsc_cfg->native_420); in intel_vdsc_set_min_max_qp()
78 calculate_rc_params(struct drm_dsc_config *vdsc_cfg) in calculate_rc_params() argument
80 int bpc = vdsc_cfg->bits_per_component; in calculate_rc_params()
81 int bpp = vdsc_cfg->bits_per_pixel >> 4; in calculate_rc_params()
85 if (vdsc_cfg in calculate_rc_params()
217 intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config, struct drm_dsc_config *vdsc_cfg) intel_dsc_slice_dimensions_valid() argument
244 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; intel_dsc_compute_params() local
367 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; intel_dsc_pps_configure() local
883 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; intel_dsc_dsi_pps_write() local
906 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; intel_dsc_dp_pps_write() local
994 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; intel_dsc_get_config() local
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H A Dicl_dsi.c1570 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in gen11_dsi_dsc_compute_config() local
1587 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; in gen11_dsi_dsc_compute_config()
1589 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; in gen11_dsi_dsc_compute_config()
1596 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); in gen11_dsi_dsc_compute_config()
1597 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); in gen11_dsi_dsc_compute_config()
1599 vdsc_cfg->pic_width % vdsc_cfg->slice_width); in gen11_dsi_dsc_compute_config()
1600 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); in gen11_dsi_dsc_compute_config()
1602 vdsc_cfg->pic_height % vdsc_cfg in gen11_dsi_dsc_compute_config()
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H A Dintel_dp.c1582 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dp_dsc_compute_params() local
1592 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; in intel_dp_dsc_compute_params()
1593 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; in intel_dp_dsc_compute_params()
1595 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height); in intel_dp_dsc_compute_params()
1601 vdsc_cfg->dsc_version_major = in intel_dp_dsc_compute_params()
1604 vdsc_cfg->dsc_version_minor = in intel_dp_dsc_compute_params()
1607 if (vdsc_cfg->convert_rgb) in intel_dp_dsc_compute_params()
1608 vdsc_cfg->convert_rgb = in intel_dp_dsc_compute_params()
1619 if (vdsc_cfg in intel_dp_dsc_compute_params()
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H A Dintel_bios.c3369 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in fill_dsc() local
3372 vdsc_cfg->dsc_version_major = dsc->version_major; in fill_dsc()
3373 vdsc_cfg->dsc_version_minor = dsc->version_minor; in fill_dsc()
3418 vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size, in fill_dsc()
3422 vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth); in fill_dsc()
3424 vdsc_cfg->block_pred_enable = dsc->block_prediction_enable; in fill_dsc()
3426 vdsc_cfg->slice_height = dsc->slice_height; in fill_dsc()
H A Dintel_psr.c964 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in psr2_granularity_check() local
996 vdsc_cfg->slice_height % y_granularity) in psr2_granularity_check()
1949 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_psr2_sel_fetch_pipe_alignment() local
1955 y_alignment = vdsc_cfg->slice_height; in intel_psr2_sel_fetch_pipe_alignment()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_vdsc.c383 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; in intel_dsc_compute_params() local
388 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; in intel_dsc_compute_params()
389 vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay; in intel_dsc_compute_params()
390 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, in intel_dsc_compute_params()
394 vdsc_cfg->simple_422 = false; in intel_dsc_compute_params()
396 vdsc_cfg->vbr_enable = false; in intel_dsc_compute_params()
399 vdsc_cfg->bits_per_pixel = compressed_bpp << 4; in intel_dsc_compute_params()
400 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
408 vdsc_cfg in intel_dsc_compute_params()
498 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; intel_dsc_pps_configure() local
980 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; intel_dsc_get_config() local
1028 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; intel_dsc_dsi_pps_write() local
1049 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; intel_dsc_dp_pps_write() local
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H A Dicl_dsi.c1479 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in gen11_dsi_dsc_compute_config() local
1495 vdsc_cfg->convert_rgb = true; in gen11_dsi_dsc_compute_config()
1502 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); in gen11_dsi_dsc_compute_config()
1503 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); in gen11_dsi_dsc_compute_config()
1505 vdsc_cfg->pic_width % vdsc_cfg->slice_width); in gen11_dsi_dsc_compute_config()
1506 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); in gen11_dsi_dsc_compute_config()
1508 vdsc_cfg->pic_height % vdsc_cfg->slice_height); in gen11_dsi_dsc_compute_config()
1510 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); in gen11_dsi_dsc_compute_config()
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H A Dintel_bios.c2486 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in fill_dsc() local
2489 vdsc_cfg->dsc_version_major = dsc->version_major; in fill_dsc()
2490 vdsc_cfg->dsc_version_minor = dsc->version_minor; in fill_dsc()
2544 vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth); in fill_dsc()
2546 vdsc_cfg->block_pred_enable = dsc->block_prediction_enable; in fill_dsc()
2548 vdsc_cfg->slice_height = dsc->slice_height; in fill_dsc()
H A Dintel_dp.c2181 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dp_dsc_compute_params() local
2194 if (vdsc_cfg->pic_height % 8 == 0) in intel_dp_dsc_compute_params()
2195 vdsc_cfg->slice_height = 8; in intel_dp_dsc_compute_params()
2196 else if (vdsc_cfg->pic_height % 4 == 0) in intel_dp_dsc_compute_params()
2197 vdsc_cfg->slice_height = 4; in intel_dp_dsc_compute_params()
2199 vdsc_cfg->slice_height = 2; in intel_dp_dsc_compute_params()
2201 vdsc_cfg->dsc_version_major = in intel_dp_dsc_compute_params()
2204 vdsc_cfg->dsc_version_minor = in intel_dp_dsc_compute_params()
2209 vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & in intel_dp_dsc_compute_params()
2219 if (vdsc_cfg in intel_dp_dsc_compute_params()
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/kernel/linux/linux-6.6/include/drm/display/
H A Ddrm_dsc_helper.h24 void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg);
25 void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
26 int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_type type);
27 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
30 u32 drm_dsc_get_bpp_int(const struct drm_dsc_config *vdsc_cfg);
/kernel/linux/linux-5.10/include/drm/
H A Ddrm_dsc.h607 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);

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