162306a36Sopenharmony_ci/* SPDX-License-Identifier: MIT 262306a36Sopenharmony_ci * Copyright (C) 2018 Intel Corp. 362306a36Sopenharmony_ci * 462306a36Sopenharmony_ci * Authors: 562306a36Sopenharmony_ci * Manasi Navare <manasi.d.navare@intel.com> 662306a36Sopenharmony_ci */ 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci#ifndef DRM_DSC_HELPER_H_ 962306a36Sopenharmony_ci#define DRM_DSC_HELPER_H_ 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci#include <drm/display/drm_dsc.h> 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_cienum drm_dsc_params_type { 1462306a36Sopenharmony_ci DRM_DSC_1_2_444, 1562306a36Sopenharmony_ci DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */ 1662306a36Sopenharmony_ci DRM_DSC_1_2_422, 1762306a36Sopenharmony_ci DRM_DSC_1_2_420, 1862306a36Sopenharmony_ci}; 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_civoid drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); 2162306a36Sopenharmony_ciint drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size); 2262306a36Sopenharmony_civoid drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, 2362306a36Sopenharmony_ci const struct drm_dsc_config *dsc_cfg); 2462306a36Sopenharmony_civoid drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg); 2562306a36Sopenharmony_civoid drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg); 2662306a36Sopenharmony_ciint drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_type type); 2762306a36Sopenharmony_ciint drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); 2862306a36Sopenharmony_ciu8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc); 2962306a36Sopenharmony_ciu32 drm_dsc_flatness_det_thresh(const struct drm_dsc_config *dsc); 3062306a36Sopenharmony_ciu32 drm_dsc_get_bpp_int(const struct drm_dsc_config *vdsc_cfg); 3162306a36Sopenharmony_ci 3262306a36Sopenharmony_ci#endif /* _DRM_DSC_HELPER_H_ */ 3362306a36Sopenharmony_ci 34