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Searched refs:train_set (Results 1 - 19 of 19) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_dp_link_training.c439 intel_dp->train_set[lane] = in intel_dp_get_adjust_train()
459 u8 buf[sizeof(intel_dp->train_set) + 1]; in intel_dp_set_link_train()
467 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); in intel_dp_set_link_train()
504 #define _TRAIN_SET_VSWING_ARGS(train_set) \
505 ((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \
506 (train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : ""
507 #define TRAIN_SET_VSWING_ARGS(train_set) \
508 _TRAIN_SET_VSWING_ARGS((train_set)[0]), \
509 _TRAIN_SET_VSWING_ARGS((train_set)[1]), \
510 _TRAIN_SET_VSWING_ARGS((train_set)[
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H A Dg4x_dp.c796 u8 train_set = intel_dp->train_set[0]; in vlv_set_signal_levels() local
798 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in vlv_set_signal_levels()
801 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
824 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
843 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
858 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
882 u8 train_set = intel_dp->train_set[0]; in chv_set_signal_levels() local
884 switch (train_set in chv_set_signal_levels()
959 g4x_signal_levels(u8 train_set) g4x_signal_levels() argument
1002 u8 train_set = intel_dp->train_set[0]; g4x_set_signal_levels() local
1018 snb_cpu_edp_signal_levels(u8 train_set) snb_cpu_edp_signal_levels() argument
1050 u8 train_set = intel_dp->train_set[0]; snb_cpu_edp_set_signal_levels() local
1066 ivb_cpu_edp_signal_levels(u8 train_set) ivb_cpu_edp_signal_levels() argument
1102 u8 train_set = intel_dp->train_set[0]; ivb_cpu_edp_set_signal_levels() local
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H A Dintel_ddi.c1412 u8 train_set = intel_dp->train_set[lane]; in intel_ddi_dp_level() local
1415 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; in intel_ddi_dp_level()
1417 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in intel_ddi_dp_level()
H A Dintel_display_types.h1743 u8 train_set[4]; member
H A Dintel_dp.c2372 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); in intel_dp_set_link_params()
3987 intel_dp->train_set, crtc_state->lane_count); in intel_dp_process_phy_request()
H A Dintel_display_debugfs.c951 intel_dp->train_set[0]); in i915_displayport_test_data_show()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_dp_link_training.c86 intel_dp->train_set[lane] = v | p; in intel_dp_get_adjust_train()
93 u8 buf[sizeof(intel_dp->train_set) + 1]; in intel_dp_set_link_train()
105 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); in intel_dp_set_link_train()
119 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); in intel_dp_reset_link_train()
132 intel_dp->train_set, intel_dp->lane_count); in intel_dp_update_link_train()
142 if ((intel_dp->train_set[lane] & in intel_dp_link_max_vswing_reached()
261 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in intel_dp_link_training_clock_recovery()
271 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == in intel_dp_link_training_clock_recovery()
H A Dintel_dp.c4181 u8 train_set = intel_dp->train_set[0]; in vlv_set_signal_levels() local
4183 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in vlv_set_signal_levels()
4186 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
4209 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
4228 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
4243 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
4265 u8 train_set = intel_dp->train_set[0]; in chv_set_signal_levels() local
4267 switch (train_set in chv_set_signal_levels()
4341 g4x_signal_levels(u8 train_set) g4x_signal_levels() argument
4382 u8 train_set = intel_dp->train_set[0]; g4x_set_signal_levels() local
4398 snb_cpu_edp_signal_levels(u8 train_set) snb_cpu_edp_signal_levels() argument
4429 u8 train_set = intel_dp->train_set[0]; snb_cpu_edp_set_signal_levels() local
4445 ivb_cpu_edp_signal_levels(u8 train_set) ivb_cpu_edp_signal_levels() argument
4480 u8 train_set = intel_dp->train_set[0]; ivb_cpu_edp_set_signal_levels() local
4498 u8 train_set = intel_dp->train_set[0]; intel_dp_set_signal_levels() local
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H A Dintel_display_types.h1303 u8 train_set[4]; member
H A Dintel_ddi.c2825 u8 train_set = intel_dp->train_set[0]; in intel_ddi_dp_level() local
2826 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in intel_ddi_dp_level()
H A Dintel_display_debugfs.c1391 intel_dp->train_set[0]); in i915_displayport_test_data_show()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Datombios_dp.c202 u8 train_set[4]) in amdgpu_atombios_dp_get_adjust_train()
234 train_set[lane] = v | p; in amdgpu_atombios_dp_get_adjust_train()
493 u8 train_set[4]; member
505 0, dp_info->train_set[0]); /* sets all lanes at once */ in amdgpu_atombios_dp_update_vs_emph()
509 dp_info->train_set, dp_info->dp_lane_count); in amdgpu_atombios_dp_update_vs_emph()
603 memset(dp_info->train_set, 0, 4); in amdgpu_atombios_dp_link_train_cr()
627 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in amdgpu_atombios_dp_link_train_cr()
635 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in amdgpu_atombios_dp_link_train_cr()
644 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in amdgpu_atombios_dp_link_train_cr()
646 /* Compute new train_set a in amdgpu_atombios_dp_link_train_cr()
200 amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], int lane_count, u8 train_set[4]) amdgpu_atombios_dp_get_adjust_train() argument
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/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Datombios_dp.c258 u8 train_set[4]) in dp_get_adjust_train()
290 train_set[lane] = v | p; in dp_get_adjust_train()
545 u8 train_set[4]; member
557 0, dp_info->train_set[0]); /* sets all lanes at once */ in radeon_dp_update_vs_emph()
561 dp_info->train_set, dp_info->dp_lane_count); in radeon_dp_update_vs_emph()
672 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()
696 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()
704 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in radeon_dp_link_train_cr()
713 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()
715 /* Compute new train_set a in radeon_dp_link_train_cr()
256 dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], int lane_count, u8 train_set[4]) dp_get_adjust_train() argument
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Datombios_dp.c205 u8 train_set[4]) in amdgpu_atombios_dp_get_adjust_train()
237 train_set[lane] = v | p; in amdgpu_atombios_dp_get_adjust_train()
496 u8 train_set[4]; member
508 0, dp_info->train_set[0]); /* sets all lanes at once */ in amdgpu_atombios_dp_update_vs_emph()
512 dp_info->train_set, dp_info->dp_lane_count); in amdgpu_atombios_dp_update_vs_emph()
606 memset(dp_info->train_set, 0, 4); in amdgpu_atombios_dp_link_train_cr()
630 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in amdgpu_atombios_dp_link_train_cr()
638 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in amdgpu_atombios_dp_link_train_cr()
647 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in amdgpu_atombios_dp_link_train_cr()
649 /* Compute new train_set a in amdgpu_atombios_dp_link_train_cr()
203 amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], int lane_count, u8 train_set[4]) amdgpu_atombios_dp_get_adjust_train() argument
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/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Datombios_dp.c259 u8 train_set[4]) in dp_get_adjust_train()
291 train_set[lane] = v | p; in dp_get_adjust_train()
546 u8 train_set[4]; member
558 0, dp_info->train_set[0]); /* sets all lanes at once */ in radeon_dp_update_vs_emph()
562 dp_info->train_set, dp_info->dp_lane_count); in radeon_dp_update_vs_emph()
673 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()
697 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()
705 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in radeon_dp_link_train_cr()
714 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()
716 /* Compute new train_set a in radeon_dp_link_train_cr()
257 dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], int lane_count, u8 train_set[4]) dp_get_adjust_train() argument
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/kernel/linux/linux-5.10/drivers/gpu/drm/xlnx/
H A Dzynqmp_dp.c297 * @train_set: set of training data
320 u8 train_set[ZYNQMP_DP_MAX_LANES]; member
614 u8 *train_set = dp->train_set; in zynqmp_dp_adjust_train() local
636 train_set[i] = voltage | preemphasis; in zynqmp_dp_adjust_train()
654 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->train_set, in zynqmp_dp_update_vs_emph()
662 u8 train = dp->train_set[i]; in zynqmp_dp_update_vs_emph()
720 if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED)) in zynqmp_dp_link_train_cr()
725 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs) in zynqmp_dp_link_train_cr()
733 vs = dp->train_set[ in zynqmp_dp_link_train_cr()
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/kernel/linux/linux-6.6/drivers/gpu/drm/xlnx/
H A Dzynqmp_dp.c295 * @train_set: set of training data
318 u8 train_set[ZYNQMP_DP_MAX_LANES]; member
607 u8 *train_set = dp->train_set; in zynqmp_dp_adjust_train() local
629 train_set[i] = voltage | preemphasis; in zynqmp_dp_adjust_train()
647 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->train_set, in zynqmp_dp_update_vs_emph()
655 u8 train = dp->train_set[i]; in zynqmp_dp_update_vs_emph()
713 if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED)) in zynqmp_dp_link_train_cr()
718 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs) in zynqmp_dp_link_train_cr()
726 vs = dp->train_set[ in zynqmp_dp_link_train_cr()
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/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c271 uint8_t train_set[4]; member
1302 intel_dp->train_set[lane] = v | p; in cdv_intel_get_adjust_train()
1393 intel_dp->train_set, in cdv_intel_dplink_set_level()
1398 intel_dp->train_set[0], intel_dp->lane_count); in cdv_intel_dplink_set_level()
1498 memset(intel_dp->train_set, 0, 4); in cdv_intel_dp_start_link_train()
1508 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ in cdv_intel_dp_start_link_train()
1510 intel_dp->train_set[0], in cdv_intel_dp_start_link_train()
1517 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); in cdv_intel_dp_start_link_train()
1538 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in cdv_intel_dp_start_link_train()
1544 if ((intel_dp->train_set[ in cdv_intel_dp_start_link_train()
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/kernel/linux/linux-6.6/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c267 uint8_t train_set[4]; member
1298 intel_dp->train_set[lane] = v | p; in cdv_intel_get_adjust_train()
1387 intel_dp->train_set, in cdv_intel_dplink_set_level()
1392 intel_dp->train_set[0], intel_dp->lane_count); in cdv_intel_dplink_set_level()
1492 memset(intel_dp->train_set, 0, 4); in cdv_intel_dp_start_link_train()
1501 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ in cdv_intel_dp_start_link_train()
1503 intel_dp->train_set[0], in cdv_intel_dp_start_link_train()
1510 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); in cdv_intel_dp_start_link_train()
1531 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in cdv_intel_dp_start_link_train()
1537 if ((intel_dp->train_set[ in cdv_intel_dp_start_link_train()
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