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Searched refs:tegra_dc_writel (Results 1 - 14 of 14) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/tegra/
H A Ddc.c54 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
56 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
93 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
123 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
124 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
950 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); in __tegra_cursor_atomic_update()
954 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); in __tegra_cursor_atomic_update()
960 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in __tegra_cursor_atomic_update()
974 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); in __tegra_cursor_atomic_update()
986 tegra_dc_writel(d in __tegra_cursor_atomic_update()
[all...]
H A Drgb.c88 tegra_dc_writel(dc, table[i].value, table[i].offset); in tegra_dc_write_regs()
109 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); in tegra_rgb_encoder_enable()
115 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); in tegra_rgb_encoder_enable()
120 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL); in tegra_rgb_encoder_enable()
H A Dhub.c110 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
201 tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL); in tegra_shared_plane_update()
221 tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL); in tegra_shared_plane_activate()
293 tegra_dc_writel(dc, value, offset); in tegra_shared_plane_set_owner()
898 tegra_dc_writel(dc, value, DC_CMD_IHUB_COMMON_MISC_CTL); in tegra_display_hub_update()
902 tegra_dc_writel(dc, value, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER); in tegra_display_hub_update()
904 tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL); in tegra_display_hub_update()
906 tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL); in tegra_display_hub_update()
H A Dhdmi.c1178 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_disable()
1256 tegra_dc_writel(dc, VSYNC_H_POSITION(1), in tegra_hdmi_encoder_enable()
1258 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888, in tegra_hdmi_encoder_enable()
1264 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_hdmi_encoder_enable()
1268 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_hdmi_encoder_enable()
1271 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_hdmi_encoder_enable()
1415 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_enable()
H A Dsor.c2228 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2453 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_sor_hdmi_enable()
2456 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_sor_hdmi_enable()
2460 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2550 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); in tegra_sor_hdmi_enable()
2580 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2625 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2631 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2681 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_disable()
2922 tegra_dc_writel(d in tegra_sor_dp_enable()
[all...]
H A Ddc.h119 static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, in tegra_dc_writel() function
H A Ddsi.c861 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_disable()
948 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_enable()
/kernel/linux/linux-5.10/drivers/gpu/drm/tegra/
H A Ddc.c47 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
49 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
86 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
116 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
117 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
898 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); in tegra_cursor_atomic_update()
902 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); in tegra_cursor_atomic_update()
908 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_update()
917 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_cursor_atomic_update()
922 tegra_dc_writel(d in tegra_cursor_atomic_update()
[all...]
H A Drgb.c85 tegra_dc_writel(dc, table[i].value, table[i].offset); in tegra_dc_write_regs()
106 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); in tegra_rgb_encoder_enable()
112 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); in tegra_rgb_encoder_enable()
117 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL); in tegra_rgb_encoder_enable()
121 tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS); in tegra_rgb_encoder_enable()
H A Dhub.c93 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
184 tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL); in tegra_shared_plane_update()
204 tegra_dc_writel(dc, mask, DC_CMD_STATE_CONTROL); in tegra_shared_plane_activate()
276 tegra_dc_writel(dc, value, offset); in tegra_shared_plane_set_owner()
691 tegra_dc_writel(dc, value, DC_CMD_IHUB_COMMON_MISC_CTL); in tegra_display_hub_update()
695 tegra_dc_writel(dc, value, DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER); in tegra_display_hub_update()
697 tegra_dc_writel(dc, COMMON_UPDATE, DC_CMD_STATE_CONTROL); in tegra_display_hub_update()
699 tegra_dc_writel(dc, COMMON_ACTREQ, DC_CMD_STATE_CONTROL); in tegra_display_hub_update()
H A Dhdmi.c1145 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_disable()
1217 tegra_dc_writel(dc, VSYNC_H_POSITION(1), in tegra_hdmi_encoder_enable()
1219 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888, in tegra_hdmi_encoder_enable()
1225 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_hdmi_encoder_enable()
1229 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_hdmi_encoder_enable()
1232 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_hdmi_encoder_enable()
1376 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_enable()
H A Dsor.c2232 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2457 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_sor_hdmi_enable()
2460 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_sor_hdmi_enable()
2464 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2554 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); in tegra_sor_hdmi_enable()
2584 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2629 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2635 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2685 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_disable()
2926 tegra_dc_writel(d in tegra_sor_dp_enable()
[all...]
H A Ddc.h106 static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, in tegra_dc_writel() function
H A Ddsi.c861 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_disable()
939 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_enable()

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