18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-only
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Copyright (C) 2012 Avionic Design GmbH
48c2ecf20Sopenharmony_ci * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
58c2ecf20Sopenharmony_ci */
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ci#include <linux/clk.h>
88c2ecf20Sopenharmony_ci
98c2ecf20Sopenharmony_ci#include <drm/drm_atomic_helper.h>
108c2ecf20Sopenharmony_ci#include <drm/drm_bridge_connector.h>
118c2ecf20Sopenharmony_ci#include <drm/drm_simple_kms_helper.h>
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_ci#include "drm.h"
148c2ecf20Sopenharmony_ci#include "dc.h"
158c2ecf20Sopenharmony_ci
168c2ecf20Sopenharmony_cistruct tegra_rgb {
178c2ecf20Sopenharmony_ci	struct tegra_output output;
188c2ecf20Sopenharmony_ci	struct tegra_dc *dc;
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_ci	struct clk *clk_parent;
218c2ecf20Sopenharmony_ci	struct clk *clk;
228c2ecf20Sopenharmony_ci};
238c2ecf20Sopenharmony_ci
248c2ecf20Sopenharmony_cistatic inline struct tegra_rgb *to_rgb(struct tegra_output *output)
258c2ecf20Sopenharmony_ci{
268c2ecf20Sopenharmony_ci	return container_of(output, struct tegra_rgb, output);
278c2ecf20Sopenharmony_ci}
288c2ecf20Sopenharmony_ci
298c2ecf20Sopenharmony_cistruct reg_entry {
308c2ecf20Sopenharmony_ci	unsigned long offset;
318c2ecf20Sopenharmony_ci	unsigned long value;
328c2ecf20Sopenharmony_ci};
338c2ecf20Sopenharmony_ci
348c2ecf20Sopenharmony_cistatic const struct reg_entry rgb_enable[] = {
358c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_ENABLE(0),   0x00000000 },
368c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_ENABLE(1),   0x00000000 },
378c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_ENABLE(2),   0x00000000 },
388c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_ENABLE(3),   0x00000000 },
398c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
408c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
418c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
428c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
438c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_DATA(0),     0x00000000 },
448c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_DATA(1),     0x00000000 },
458c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_DATA(2),     0x00000000 },
468c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_DATA(3),     0x00000000 },
478c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_SELECT(0),   0x00000000 },
488c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_SELECT(1),   0x00000000 },
498c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_SELECT(2),   0x00000000 },
508c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_SELECT(3),   0x00000000 },
518c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_SELECT(4),   0x00210222 },
528c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_SELECT(5),   0x00002200 },
538c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_SELECT(6),   0x00020000 },
548c2ecf20Sopenharmony_ci};
558c2ecf20Sopenharmony_ci
568c2ecf20Sopenharmony_cistatic const struct reg_entry rgb_disable[] = {
578c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_SELECT(6),   0x00000000 },
588c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_SELECT(5),   0x00000000 },
598c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_SELECT(4),   0x00000000 },
608c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_SELECT(3),   0x00000000 },
618c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_SELECT(2),   0x00000000 },
628c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_SELECT(1),   0x00000000 },
638c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_SELECT(0),   0x00000000 },
648c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_DATA(3),     0xaaaaaaaa },
658c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_DATA(2),     0xaaaaaaaa },
668c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_DATA(1),     0xaaaaaaaa },
678c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_DATA(0),     0xaaaaaaaa },
688c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
698c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
708c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 },
718c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
728c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_ENABLE(3),   0x55555555 },
738c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_ENABLE(2),   0x55555555 },
748c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_ENABLE(1),   0x55150005 },
758c2ecf20Sopenharmony_ci	{ DC_COM_PIN_OUTPUT_ENABLE(0),   0x55555555 },
768c2ecf20Sopenharmony_ci};
778c2ecf20Sopenharmony_ci
788c2ecf20Sopenharmony_cistatic void tegra_dc_write_regs(struct tegra_dc *dc,
798c2ecf20Sopenharmony_ci				const struct reg_entry *table,
808c2ecf20Sopenharmony_ci				unsigned int num)
818c2ecf20Sopenharmony_ci{
828c2ecf20Sopenharmony_ci	unsigned int i;
838c2ecf20Sopenharmony_ci
848c2ecf20Sopenharmony_ci	for (i = 0; i < num; i++)
858c2ecf20Sopenharmony_ci		tegra_dc_writel(dc, table[i].value, table[i].offset);
868c2ecf20Sopenharmony_ci}
878c2ecf20Sopenharmony_ci
888c2ecf20Sopenharmony_cistatic void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
898c2ecf20Sopenharmony_ci{
908c2ecf20Sopenharmony_ci	struct tegra_output *output = encoder_to_output(encoder);
918c2ecf20Sopenharmony_ci	struct tegra_rgb *rgb = to_rgb(output);
928c2ecf20Sopenharmony_ci
938c2ecf20Sopenharmony_ci	tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
948c2ecf20Sopenharmony_ci	tegra_dc_commit(rgb->dc);
958c2ecf20Sopenharmony_ci}
968c2ecf20Sopenharmony_ci
978c2ecf20Sopenharmony_cistatic void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
988c2ecf20Sopenharmony_ci{
998c2ecf20Sopenharmony_ci	struct tegra_output *output = encoder_to_output(encoder);
1008c2ecf20Sopenharmony_ci	struct tegra_rgb *rgb = to_rgb(output);
1018c2ecf20Sopenharmony_ci	u32 value;
1028c2ecf20Sopenharmony_ci
1038c2ecf20Sopenharmony_ci	tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
1048c2ecf20Sopenharmony_ci
1058c2ecf20Sopenharmony_ci	value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
1068c2ecf20Sopenharmony_ci	tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
1078c2ecf20Sopenharmony_ci
1088c2ecf20Sopenharmony_ci	/* XXX: parameterize? */
1098c2ecf20Sopenharmony_ci	value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
1108c2ecf20Sopenharmony_ci	value &= ~LVS_OUTPUT_POLARITY_LOW;
1118c2ecf20Sopenharmony_ci	value &= ~LHS_OUTPUT_POLARITY_LOW;
1128c2ecf20Sopenharmony_ci	tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
1138c2ecf20Sopenharmony_ci
1148c2ecf20Sopenharmony_ci	/* XXX: parameterize? */
1158c2ecf20Sopenharmony_ci	value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
1168c2ecf20Sopenharmony_ci		DISP_ORDER_RED_BLUE;
1178c2ecf20Sopenharmony_ci	tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
1188c2ecf20Sopenharmony_ci
1198c2ecf20Sopenharmony_ci	/* XXX: parameterize? */
1208c2ecf20Sopenharmony_ci	value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
1218c2ecf20Sopenharmony_ci	tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
1228c2ecf20Sopenharmony_ci
1238c2ecf20Sopenharmony_ci	tegra_dc_commit(rgb->dc);
1248c2ecf20Sopenharmony_ci}
1258c2ecf20Sopenharmony_ci
1268c2ecf20Sopenharmony_cistatic int
1278c2ecf20Sopenharmony_citegra_rgb_encoder_atomic_check(struct drm_encoder *encoder,
1288c2ecf20Sopenharmony_ci			       struct drm_crtc_state *crtc_state,
1298c2ecf20Sopenharmony_ci			       struct drm_connector_state *conn_state)
1308c2ecf20Sopenharmony_ci{
1318c2ecf20Sopenharmony_ci	struct tegra_output *output = encoder_to_output(encoder);
1328c2ecf20Sopenharmony_ci	struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1338c2ecf20Sopenharmony_ci	unsigned long pclk = crtc_state->mode.clock * 1000;
1348c2ecf20Sopenharmony_ci	struct tegra_rgb *rgb = to_rgb(output);
1358c2ecf20Sopenharmony_ci	unsigned int div;
1368c2ecf20Sopenharmony_ci	int err;
1378c2ecf20Sopenharmony_ci
1388c2ecf20Sopenharmony_ci	/*
1398c2ecf20Sopenharmony_ci	 * We may not want to change the frequency of the parent clock, since
1408c2ecf20Sopenharmony_ci	 * it may be a parent for other peripherals. This is due to the fact
1418c2ecf20Sopenharmony_ci	 * that on Tegra20 there's only a single clock dedicated to display
1428c2ecf20Sopenharmony_ci	 * (pll_d_out0), whereas later generations have a second one that can
1438c2ecf20Sopenharmony_ci	 * be used to independently drive a second output (pll_d2_out0).
1448c2ecf20Sopenharmony_ci	 *
1458c2ecf20Sopenharmony_ci	 * As a way to support multiple outputs on Tegra20 as well, pll_p is
1468c2ecf20Sopenharmony_ci	 * typically used as the parent clock for the display controllers.
1478c2ecf20Sopenharmony_ci	 * But this comes at a cost: pll_p is the parent of several other
1488c2ecf20Sopenharmony_ci	 * peripherals, so its frequency shouldn't change out of the blue.
1498c2ecf20Sopenharmony_ci	 *
1508c2ecf20Sopenharmony_ci	 * The best we can do at this point is to use the shift clock divider
1518c2ecf20Sopenharmony_ci	 * and hope that the desired frequency can be matched (or at least
1528c2ecf20Sopenharmony_ci	 * matched sufficiently close that the panel will still work).
1538c2ecf20Sopenharmony_ci	 */
1548c2ecf20Sopenharmony_ci	div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2;
1558c2ecf20Sopenharmony_ci	pclk = 0;
1568c2ecf20Sopenharmony_ci
1578c2ecf20Sopenharmony_ci	err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent,
1588c2ecf20Sopenharmony_ci					 pclk, div);
1598c2ecf20Sopenharmony_ci	if (err < 0) {
1608c2ecf20Sopenharmony_ci		dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1618c2ecf20Sopenharmony_ci		return err;
1628c2ecf20Sopenharmony_ci	}
1638c2ecf20Sopenharmony_ci
1648c2ecf20Sopenharmony_ci	return err;
1658c2ecf20Sopenharmony_ci}
1668c2ecf20Sopenharmony_ci
1678c2ecf20Sopenharmony_cistatic const struct drm_encoder_helper_funcs tegra_rgb_encoder_helper_funcs = {
1688c2ecf20Sopenharmony_ci	.disable = tegra_rgb_encoder_disable,
1698c2ecf20Sopenharmony_ci	.enable = tegra_rgb_encoder_enable,
1708c2ecf20Sopenharmony_ci	.atomic_check = tegra_rgb_encoder_atomic_check,
1718c2ecf20Sopenharmony_ci};
1728c2ecf20Sopenharmony_ci
1738c2ecf20Sopenharmony_ciint tegra_dc_rgb_probe(struct tegra_dc *dc)
1748c2ecf20Sopenharmony_ci{
1758c2ecf20Sopenharmony_ci	struct device_node *np;
1768c2ecf20Sopenharmony_ci	struct tegra_rgb *rgb;
1778c2ecf20Sopenharmony_ci	int err;
1788c2ecf20Sopenharmony_ci
1798c2ecf20Sopenharmony_ci	np = of_get_child_by_name(dc->dev->of_node, "rgb");
1808c2ecf20Sopenharmony_ci	if (!np || !of_device_is_available(np))
1818c2ecf20Sopenharmony_ci		return -ENODEV;
1828c2ecf20Sopenharmony_ci
1838c2ecf20Sopenharmony_ci	rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
1848c2ecf20Sopenharmony_ci	if (!rgb)
1858c2ecf20Sopenharmony_ci		return -ENOMEM;
1868c2ecf20Sopenharmony_ci
1878c2ecf20Sopenharmony_ci	rgb->output.dev = dc->dev;
1888c2ecf20Sopenharmony_ci	rgb->output.of_node = np;
1898c2ecf20Sopenharmony_ci	rgb->dc = dc;
1908c2ecf20Sopenharmony_ci
1918c2ecf20Sopenharmony_ci	err = tegra_output_probe(&rgb->output);
1928c2ecf20Sopenharmony_ci	if (err < 0)
1938c2ecf20Sopenharmony_ci		return err;
1948c2ecf20Sopenharmony_ci
1958c2ecf20Sopenharmony_ci	rgb->clk = devm_clk_get(dc->dev, NULL);
1968c2ecf20Sopenharmony_ci	if (IS_ERR(rgb->clk)) {
1978c2ecf20Sopenharmony_ci		dev_err(dc->dev, "failed to get clock\n");
1988c2ecf20Sopenharmony_ci		return PTR_ERR(rgb->clk);
1998c2ecf20Sopenharmony_ci	}
2008c2ecf20Sopenharmony_ci
2018c2ecf20Sopenharmony_ci	rgb->clk_parent = devm_clk_get(dc->dev, "parent");
2028c2ecf20Sopenharmony_ci	if (IS_ERR(rgb->clk_parent)) {
2038c2ecf20Sopenharmony_ci		dev_err(dc->dev, "failed to get parent clock\n");
2048c2ecf20Sopenharmony_ci		return PTR_ERR(rgb->clk_parent);
2058c2ecf20Sopenharmony_ci	}
2068c2ecf20Sopenharmony_ci
2078c2ecf20Sopenharmony_ci	err = clk_set_parent(rgb->clk, rgb->clk_parent);
2088c2ecf20Sopenharmony_ci	if (err < 0) {
2098c2ecf20Sopenharmony_ci		dev_err(dc->dev, "failed to set parent clock: %d\n", err);
2108c2ecf20Sopenharmony_ci		return err;
2118c2ecf20Sopenharmony_ci	}
2128c2ecf20Sopenharmony_ci
2138c2ecf20Sopenharmony_ci	dc->rgb = &rgb->output;
2148c2ecf20Sopenharmony_ci
2158c2ecf20Sopenharmony_ci	return 0;
2168c2ecf20Sopenharmony_ci}
2178c2ecf20Sopenharmony_ci
2188c2ecf20Sopenharmony_ciint tegra_dc_rgb_remove(struct tegra_dc *dc)
2198c2ecf20Sopenharmony_ci{
2208c2ecf20Sopenharmony_ci	if (!dc->rgb)
2218c2ecf20Sopenharmony_ci		return 0;
2228c2ecf20Sopenharmony_ci
2238c2ecf20Sopenharmony_ci	tegra_output_remove(dc->rgb);
2248c2ecf20Sopenharmony_ci	dc->rgb = NULL;
2258c2ecf20Sopenharmony_ci
2268c2ecf20Sopenharmony_ci	return 0;
2278c2ecf20Sopenharmony_ci}
2288c2ecf20Sopenharmony_ci
2298c2ecf20Sopenharmony_ciint tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
2308c2ecf20Sopenharmony_ci{
2318c2ecf20Sopenharmony_ci	struct tegra_output *output = dc->rgb;
2328c2ecf20Sopenharmony_ci	struct drm_connector *connector;
2338c2ecf20Sopenharmony_ci	int err;
2348c2ecf20Sopenharmony_ci
2358c2ecf20Sopenharmony_ci	if (!dc->rgb)
2368c2ecf20Sopenharmony_ci		return -ENODEV;
2378c2ecf20Sopenharmony_ci
2388c2ecf20Sopenharmony_ci	drm_simple_encoder_init(drm, &output->encoder, DRM_MODE_ENCODER_LVDS);
2398c2ecf20Sopenharmony_ci	drm_encoder_helper_add(&output->encoder,
2408c2ecf20Sopenharmony_ci			       &tegra_rgb_encoder_helper_funcs);
2418c2ecf20Sopenharmony_ci
2428c2ecf20Sopenharmony_ci	/*
2438c2ecf20Sopenharmony_ci	 * Wrap directly-connected panel into DRM bridge in order to let
2448c2ecf20Sopenharmony_ci	 * DRM core to handle panel for us.
2458c2ecf20Sopenharmony_ci	 */
2468c2ecf20Sopenharmony_ci	if (output->panel) {
2478c2ecf20Sopenharmony_ci		output->bridge = devm_drm_panel_bridge_add(output->dev,
2488c2ecf20Sopenharmony_ci							   output->panel);
2498c2ecf20Sopenharmony_ci		if (IS_ERR(output->bridge)) {
2508c2ecf20Sopenharmony_ci			dev_err(output->dev,
2518c2ecf20Sopenharmony_ci				"failed to wrap panel into bridge: %pe\n",
2528c2ecf20Sopenharmony_ci				output->bridge);
2538c2ecf20Sopenharmony_ci			return PTR_ERR(output->bridge);
2548c2ecf20Sopenharmony_ci		}
2558c2ecf20Sopenharmony_ci
2568c2ecf20Sopenharmony_ci		output->panel = NULL;
2578c2ecf20Sopenharmony_ci	}
2588c2ecf20Sopenharmony_ci
2598c2ecf20Sopenharmony_ci	/*
2608c2ecf20Sopenharmony_ci	 * Tegra devices that have LVDS panel utilize LVDS encoder bridge
2618c2ecf20Sopenharmony_ci	 * for converting up to 28 LCD LVTTL lanes into 5/4 LVDS lanes that
2628c2ecf20Sopenharmony_ci	 * go to display panel's receiver.
2638c2ecf20Sopenharmony_ci	 *
2648c2ecf20Sopenharmony_ci	 * Encoder usually have a power-down control which needs to be enabled
2658c2ecf20Sopenharmony_ci	 * in order to transmit data to the panel.  Historically devices that
2668c2ecf20Sopenharmony_ci	 * use an older device-tree version didn't model the bridge, assuming
2678c2ecf20Sopenharmony_ci	 * that encoder is turned ON by default, while today's DRM allows us
2688c2ecf20Sopenharmony_ci	 * to model LVDS encoder properly.
2698c2ecf20Sopenharmony_ci	 *
2708c2ecf20Sopenharmony_ci	 * Newer device-trees utilize LVDS encoder bridge, which provides
2718c2ecf20Sopenharmony_ci	 * us with a connector and handles the display panel.
2728c2ecf20Sopenharmony_ci	 *
2738c2ecf20Sopenharmony_ci	 * For older device-trees we wrapped panel into the panel-bridge.
2748c2ecf20Sopenharmony_ci	 */
2758c2ecf20Sopenharmony_ci	if (output->bridge) {
2768c2ecf20Sopenharmony_ci		err = drm_bridge_attach(&output->encoder, output->bridge,
2778c2ecf20Sopenharmony_ci					NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
2788c2ecf20Sopenharmony_ci		if (err) {
2798c2ecf20Sopenharmony_ci			dev_err(output->dev, "failed to attach bridge: %d\n",
2808c2ecf20Sopenharmony_ci				err);
2818c2ecf20Sopenharmony_ci			return err;
2828c2ecf20Sopenharmony_ci		}
2838c2ecf20Sopenharmony_ci
2848c2ecf20Sopenharmony_ci		connector = drm_bridge_connector_init(drm, &output->encoder);
2858c2ecf20Sopenharmony_ci		if (IS_ERR(connector)) {
2868c2ecf20Sopenharmony_ci			dev_err(output->dev,
2878c2ecf20Sopenharmony_ci				"failed to initialize bridge connector: %pe\n",
2888c2ecf20Sopenharmony_ci				connector);
2898c2ecf20Sopenharmony_ci			return PTR_ERR(connector);
2908c2ecf20Sopenharmony_ci		}
2918c2ecf20Sopenharmony_ci
2928c2ecf20Sopenharmony_ci		drm_connector_attach_encoder(connector, &output->encoder);
2938c2ecf20Sopenharmony_ci	}
2948c2ecf20Sopenharmony_ci
2958c2ecf20Sopenharmony_ci	err = tegra_output_init(drm, output);
2968c2ecf20Sopenharmony_ci	if (err < 0) {
2978c2ecf20Sopenharmony_ci		dev_err(output->dev, "failed to initialize output: %d\n", err);
2988c2ecf20Sopenharmony_ci		return err;
2998c2ecf20Sopenharmony_ci	}
3008c2ecf20Sopenharmony_ci
3018c2ecf20Sopenharmony_ci	/*
3028c2ecf20Sopenharmony_ci	 * Other outputs can be attached to either display controller. The RGB
3038c2ecf20Sopenharmony_ci	 * outputs are an exception and work only with their parent display
3048c2ecf20Sopenharmony_ci	 * controller.
3058c2ecf20Sopenharmony_ci	 */
3068c2ecf20Sopenharmony_ci	output->encoder.possible_crtcs = drm_crtc_mask(&dc->base);
3078c2ecf20Sopenharmony_ci
3088c2ecf20Sopenharmony_ci	return 0;
3098c2ecf20Sopenharmony_ci}
3108c2ecf20Sopenharmony_ci
3118c2ecf20Sopenharmony_ciint tegra_dc_rgb_exit(struct tegra_dc *dc)
3128c2ecf20Sopenharmony_ci{
3138c2ecf20Sopenharmony_ci	if (dc->rgb)
3148c2ecf20Sopenharmony_ci		tegra_output_exit(dc->rgb);
3158c2ecf20Sopenharmony_ci
3168c2ecf20Sopenharmony_ci	return 0;
3178c2ecf20Sopenharmony_ci}
318