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Searched refs:sh_num (Results 1 - 25 of 38) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dsoc21.c272 u32 sh_num, u32 reg_offset) in soc21_read_indexed_register()
277 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc21_read_indexed_register()
278 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in soc21_read_indexed_register()
282 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc21_read_indexed_register()
290 u32 sh_num, u32 reg_offset) in soc21_get_register_value()
293 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc21_get_register_value()
302 u32 sh_num, u32 reg_offset, u32 *value) in soc21_read_register()
318 se_num, sh_num, reg_offset); in soc21_read_register()
271 soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset) soc21_read_indexed_register() argument
288 soc21_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) soc21_get_register_value() argument
301 soc21_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) soc21_read_register() argument
H A Dnv.c359 u32 sh_num, u32 reg_offset) in nv_read_indexed_register()
364 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
365 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in nv_read_indexed_register()
369 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
377 u32 sh_num, u32 reg_offset) in nv_get_register_value()
380 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
389 u32 sh_num, u32 reg_offset, u32 *value) in nv_read_register()
405 se_num, sh_num, reg_offset); in nv_read_register()
358 nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset) nv_read_indexed_register() argument
375 nv_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) nv_get_register_value() argument
388 nv_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) nv_read_register() argument
H A Dgfx_v9_0.h29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
H A Dsoc15.c381 u32 sh_num, u32 reg_offset) in soc15_read_indexed_register()
386 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
387 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in soc15_read_indexed_register()
391 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
399 u32 sh_num, u32 reg_offset) in soc15_get_register_value()
402 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
413 u32 sh_num, u32 reg_offset, u32 *value) in soc15_read_register()
429 se_num, sh_num, reg_offset); in soc15_read_register()
380 soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset) soc15_read_indexed_register() argument
397 soc15_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) soc15_get_register_value() argument
412 soc15_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) soc15_read_register() argument
H A Dcik.c1124 u32 sh_num, u32 reg_offset) in cik_get_register_value()
1129 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in cik_get_register_value()
1143 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1144 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in cik_get_register_value()
1148 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1219 u32 sh_num, u32 reg_offset, u32 *value) in cik_read_register()
1230 *value = cik_get_register_value(adev, indexed, se_num, sh_num, in cik_read_register()
1122 cik_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) cik_get_register_value() argument
1218 cik_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) cik_read_register() argument
H A Dvi.c747 u32 sh_num, u32 reg_offset) in vi_get_register_value()
752 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in vi_get_register_value()
766 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
767 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in vi_get_register_value()
771 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
842 u32 sh_num, u32 reg_offset, u32 *value) in vi_read_register()
853 *value = vi_get_register_value(adev, indexed, se_num, sh_num, in vi_read_register()
745 vi_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) vi_get_register_value() argument
841 vi_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) vi_read_register() argument
H A Dsi.c1166 u32 sh_num, u32 reg_offset) in si_get_register_value()
1171 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in si_get_register_value()
1183 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1184 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in si_get_register_value()
1188 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1240 u32 sh_num, u32 reg_offset, u32 *value) in si_read_register()
1251 *value = si_get_register_value(adev, indexed, se_num, sh_num, in si_read_register()
1164 si_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) si_get_register_value() argument
1239 si_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) si_read_register() argument
H A Damdgpu_kms.c730 unsigned int sh_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl() local
741 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) in amdgpu_info_ioctl()
742 sh_num = 0xffffffff; in amdgpu_info_ioctl()
743 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) in amdgpu_info_ioctl()
756 if (amdgpu_asic_read_register(adev, se_num, sh_num, in amdgpu_info_ioctl()
H A Dgfx_v9_4.c94 u32 sh_num, u32 instance) in gfx_v9_4_select_se_sh()
111 if (sh_num == 0xffffffff) in gfx_v9_4_select_se_sh()
115 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_select_se_sh()
93 gfx_v9_4_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) gfx_v9_4_select_se_sh() argument
H A Damdgpu_gfx.h286 u32 sh_num, u32 instance, int xcc_id);
H A Dgfx_v6_0.c1288 u32 sh_num, u32 instance, int xcc_id) in gfx_v6_0_select_se_sh()
1297 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1302 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
1303 else if (sh_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1307 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | in gfx_v6_0_select_se_sh()
1287 gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance, int xcc_id) gfx_v6_0_select_se_sh() argument
H A Dgfx_v9_4_2.c850 u32 sh_num, u32 instance) in gfx_v9_4_2_select_se_sh()
867 if (sh_num == 0xffffffff) in gfx_v9_4_2_select_se_sh()
871 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_2_select_se_sh()
849 gfx_v9_4_2_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) gfx_v9_4_2_select_se_sh() argument
H A Dgfx_v7_0.c1546 * @sh_num: sh block to address
1553 u32 se_num, u32 sh_num, u32 instance, in gfx_v7_0_select_se_sh()
1563 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v7_0_select_se_sh()
1568 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); in gfx_v7_0_select_se_sh()
1569 else if (sh_num == 0xffffffff) in gfx_v7_0_select_se_sh()
1573 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | in gfx_v7_0_select_se_sh()
1552 gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance, int xcc_id) gfx_v7_0_select_se_sh() argument
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dnv.c219 u32 sh_num, u32 reg_offset) in nv_read_indexed_register()
224 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
225 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in nv_read_indexed_register()
229 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
237 u32 sh_num, u32 reg_offset) in nv_get_register_value()
240 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
249 u32 sh_num, u32 reg_offset, u32 *value) in nv_read_register()
263 se_num, sh_num, reg_offset); in nv_read_register()
218 nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset) nv_read_indexed_register() argument
235 nv_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) nv_get_register_value() argument
248 nv_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) nv_read_register() argument
H A Dgfx_v9_0.h29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
H A Dsoc15.c345 u32 sh_num, u32 reg_offset) in soc15_read_indexed_register()
350 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
351 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in soc15_read_indexed_register()
355 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
363 u32 sh_num, u32 reg_offset) in soc15_get_register_value()
366 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
377 u32 sh_num, u32 reg_offset, u32 *value) in soc15_read_register()
393 se_num, sh_num, reg_offset); in soc15_read_register()
344 soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset) soc15_read_indexed_register() argument
361 soc15_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) soc15_get_register_value() argument
376 soc15_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) soc15_read_register() argument
H A Dvi.c539 u32 sh_num, u32 reg_offset) in vi_get_register_value()
544 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in vi_get_register_value()
558 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
559 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in vi_get_register_value()
563 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
634 u32 sh_num, u32 reg_offset, u32 *value) in vi_read_register()
645 *value = vi_get_register_value(adev, indexed, se_num, sh_num, in vi_read_register()
537 vi_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) vi_get_register_value() argument
633 vi_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) vi_read_register() argument
H A Dcik.c1048 u32 sh_num, u32 reg_offset) in cik_get_register_value()
1053 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in cik_get_register_value()
1067 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1068 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in cik_get_register_value()
1072 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1143 u32 sh_num, u32 reg_offset, u32 *value) in cik_read_register()
1154 *value = cik_get_register_value(adev, indexed, se_num, sh_num, in cik_read_register()
1046 cik_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) cik_get_register_value() argument
1142 cik_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) cik_read_register() argument
H A Dsi.c1056 u32 sh_num, u32 reg_offset) in si_get_register_value()
1061 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in si_get_register_value()
1073 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1074 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in si_get_register_value()
1078 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1130 u32 sh_num, u32 reg_offset, u32 *value) in si_read_register()
1141 *value = si_get_register_value(adev, indexed, se_num, sh_num, in si_read_register()
1054 si_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) si_get_register_value() argument
1129 si_read_register(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 reg_offset, u32 *value) si_read_register() argument
H A Damdgpu_kms.c680 unsigned int sh_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl() local
691 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) in amdgpu_info_ioctl()
692 sh_num = 0xffffffff; in amdgpu_info_ioctl()
693 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) in amdgpu_info_ioctl()
706 if (amdgpu_asic_read_register(adev, se_num, sh_num, in amdgpu_info_ioctl()
H A Damdgpu_gfx.h205 u32 sh_num, u32 instance);
H A Dgfx_v9_4.c94 u32 sh_num, u32 instance) in gfx_v9_4_select_se_sh()
111 if (sh_num == 0xffffffff) in gfx_v9_4_select_se_sh()
115 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_select_se_sh()
93 gfx_v9_4_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) gfx_v9_4_select_se_sh() argument
H A Dgfx_v6_0.c1302 u32 sh_num, u32 instance) in gfx_v6_0_select_se_sh()
1311 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1316 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
1317 else if (sh_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1321 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | in gfx_v6_0_select_se_sh()
1301 gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) gfx_v6_0_select_se_sh() argument
H A Dgfx_v7_0.c1582 * @sh_num: sh block to address
1589 u32 se_num, u32 sh_num, u32 instance) in gfx_v7_0_select_se_sh()
1598 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v7_0_select_se_sh()
1603 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); in gfx_v7_0_select_se_sh()
1604 else if (sh_num == 0xffffffff) in gfx_v7_0_select_se_sh()
1608 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | in gfx_v7_0_select_se_sh()
1588 gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) gfx_v7_0_select_se_sh() argument
H A Damdgpu.h592 u32 sh_num, u32 reg_offset, u32 *value);

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