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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dsoc21.c271 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc21_read_indexed_register() argument
277 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc21_read_indexed_register()
278 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in soc21_read_indexed_register()
282 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc21_read_indexed_register()
289 bool indexed, u32 se_num, in soc21_get_register_value()
293 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc21_get_register_value()
301 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, in soc21_read_register() argument
318 se_num, sh_num, reg_offset); in soc21_read_register()
288 soc21_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) soc21_get_register_value() argument
H A Dnv.c358 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in nv_read_indexed_register() argument
364 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
365 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in nv_read_indexed_register()
369 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
376 bool indexed, u32 se_num, in nv_get_register_value()
380 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
388 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, in nv_read_register() argument
405 se_num, sh_num, reg_offset); in nv_read_register()
375 nv_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) nv_get_register_value() argument
H A Dgfx_v9_0.h29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
H A Dsoc15.c380 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_indexed_register() argument
386 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
387 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in soc15_read_indexed_register()
391 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
398 bool indexed, u32 se_num, in soc15_get_register_value()
402 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
412 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_register() argument
429 se_num, sh_num, reg_offset); in soc15_read_register()
397 soc15_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) soc15_get_register_value() argument
H A Dgfx_v9_4.c93 static void gfx_v9_4_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v9_4_select_se_sh() argument
105 if (se_num == 0xffffffff) in gfx_v9_4_select_se_sh()
109 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_select_se_sh()
883 for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) { in gfx_v9_4_query_ras_error_count()
917 for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) { in gfx_v9_4_reset_ras_error_count()
986 for (i = 0; i < gfx_v9_4_ea_err_status_regs.se_num; i++) { in gfx_v9_4_query_ras_error_status()
H A Dsoc15.h65 uint32_t se_num; member
H A Dcik.c1123 bool indexed, u32 se_num, in cik_get_register_value()
1128 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; in cik_get_register_value()
1143 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1144 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in cik_get_register_value()
1148 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1218 static int cik_read_register(struct amdgpu_device *adev, u32 se_num, in cik_read_register() argument
1230 *value = cik_get_register_value(adev, indexed, se_num, sh_num, in cik_read_register()
1122 cik_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) cik_get_register_value() argument
H A Dvi.c746 bool indexed, u32 se_num, in vi_get_register_value()
751 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; in vi_get_register_value()
766 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
767 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in vi_get_register_value()
771 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
841 static int vi_read_register(struct amdgpu_device *adev, u32 se_num, in vi_read_register() argument
853 *value = vi_get_register_value(adev, indexed, se_num, sh_num, in vi_read_register()
745 vi_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) vi_get_register_value() argument
H A Damdgpu_gfx.h285 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
447 uint32_t se_num; member
H A Dsi.c1165 bool indexed, u32 se_num, in si_get_register_value()
1170 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; in si_get_register_value()
1183 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1184 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in si_get_register_value()
1188 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1239 static int si_read_register(struct amdgpu_device *adev, u32 se_num, in si_read_register() argument
1251 *value = si_get_register_value(adev, indexed, se_num, sh_num, in si_read_register()
1164 si_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) si_get_register_value() argument
H A Damdgpu_kms.c727 unsigned int se_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl() local
737 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) in amdgpu_info_ioctl()
738 se_num = 0xffffffff; in amdgpu_info_ioctl()
739 else if (se_num >= AMDGPU_GFX_MAX_SE) in amdgpu_info_ioctl()
756 if (amdgpu_asic_read_register(adev, se_num, sh_num, in amdgpu_info_ioctl()
H A Dgfx_v9_4_2.c849 static void gfx_v9_4_2_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v9_4_2_select_se_sh() argument
861 if (se_num == 0xffffffff) in gfx_v9_4_2_select_se_sh()
865 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_2_select_se_sh()
1505 for (j = 0; j < gfx_v9_4_2_edc_counter_regs[i].se_num; j++) { in gfx_v9_4_2_query_sram_edc_count()
1682 for (i = 0; i < gfx_v9_4_2_ea_err_status_regs.se_num; i++) { in gfx_v9_4_2_reset_ea_err_status()
1712 for (i = 0; i < gfx_v9_4_2_ea_err_status_regs.se_num; i++) { in gfx_v9_4_2_query_ea_err_status()
H A Dgfx_v9_4_3.c523 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v9_4_3_xcc_select_se_sh() argument
535 if (se_num == 0xffffffff) in gfx_v9_4_3_xcc_select_se_sh()
539 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_3_xcc_select_se_sh()
3772 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { in gfx_v9_4_3_inst_query_ras_err_count()
3775 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || in gfx_v9_4_3_inst_query_ras_err_count()
3819 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { in gfx_v9_4_3_inst_reset_ras_err_count()
3822 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || in gfx_v9_4_3_inst_reset_ras_err_count()
3852 for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) { in gfx_v9_4_3_inst_query_ea_err_status()
4001 for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) { in gfx_v9_4_3_inst_reset_ea_err_status()
H A Dgfx_v6_0.c1287 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v6_0_select_se_sh() argument
1297 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1300 else if (se_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1305 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
1308 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dnv.c218 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in nv_read_indexed_register() argument
224 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
225 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in nv_read_indexed_register()
229 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
236 bool indexed, u32 se_num, in nv_get_register_value()
240 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
248 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, in nv_read_register() argument
263 se_num, sh_num, reg_offset); in nv_read_register()
235 nv_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) nv_get_register_value() argument
H A Dgfx_v9_0.h29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
H A Dsoc15.c344 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_indexed_register() argument
350 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
351 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in soc15_read_indexed_register()
355 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
362 bool indexed, u32 se_num, in soc15_get_register_value()
366 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
376 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_register() argument
393 se_num, sh_num, reg_offset); in soc15_read_register()
361 soc15_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) soc15_get_register_value() argument
H A Dvi.c538 bool indexed, u32 se_num, in vi_get_register_value()
543 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; in vi_get_register_value()
558 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
559 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in vi_get_register_value()
563 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
633 static int vi_read_register(struct amdgpu_device *adev, u32 se_num, in vi_read_register() argument
645 *value = vi_get_register_value(adev, indexed, se_num, sh_num, in vi_read_register()
537 vi_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) vi_get_register_value() argument
H A Dsoc15.h58 uint32_t se_num; member
H A Dgfx_v9_4.c93 static void gfx_v9_4_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v9_4_select_se_sh() argument
105 if (se_num == 0xffffffff) in gfx_v9_4_select_se_sh()
109 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_select_se_sh()
883 for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) { in gfx_v9_4_query_ras_error_count()
918 for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) { in gfx_v9_4_reset_ras_error_count()
1009 for (i = 0; i < gfx_v9_4_rdrsp_status_regs.se_num; i++) { in gfx_v9_4_query_ras_error_status()
H A Dcik.c1047 bool indexed, u32 se_num, in cik_get_register_value()
1052 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; in cik_get_register_value()
1067 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1068 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in cik_get_register_value()
1072 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1142 static int cik_read_register(struct amdgpu_device *adev, u32 se_num, in cik_read_register() argument
1154 *value = cik_get_register_value(adev, indexed, se_num, sh_num, in cik_read_register()
1046 cik_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) cik_get_register_value() argument
H A Dsi.c1055 bool indexed, u32 se_num, in si_get_register_value()
1060 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; in si_get_register_value()
1073 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1074 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); in si_get_register_value()
1078 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1129 static int si_read_register(struct amdgpu_device *adev, u32 se_num, in si_read_register() argument
1141 *value = si_get_register_value(adev, indexed, se_num, sh_num, in si_read_register()
1054 si_get_register_value(struct amdgpu_device *adev, bool indexed, u32 se_num, u32 sh_num, u32 reg_offset) si_get_register_value() argument
H A Damdgpu_kms.c677 unsigned int se_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl() local
687 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) in amdgpu_info_ioctl()
688 se_num = 0xffffffff; in amdgpu_info_ioctl()
689 else if (se_num >= AMDGPU_GFX_MAX_SE) in amdgpu_info_ioctl()
706 if (amdgpu_asic_read_register(adev, se_num, sh_num, in amdgpu_info_ioctl()
H A Damdgpu_gfx.h204 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
H A Dgfx_v6_0.c1301 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, in gfx_v6_0_select_se_sh() argument
1311 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1314 else if (se_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1319 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
1322 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); in gfx_v6_0_select_se_sh()

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