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Searched refs:rb_bufsz (Results 1 - 25 of 82) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ih.c44 u32 rb_bufsz; in amdgpu_ih_ring_init() local
48 rb_bufsz = order_base_2(ring_size / 4); in amdgpu_ih_ring_init()
49 ring_size = (1 << rb_bufsz) * 4; in amdgpu_ih_ring_init()
H A Duvd_v4_2.c255 uint32_t rb_bufsz; in uvd_v4_2_start() local
365 rb_bufsz = order_base_2(ring->ring_size); in uvd_v4_2_start()
366 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v4_2_start()
367 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v4_2_start()
H A Duvd_v3_1.c319 uint32_t rb_bufsz; in uvd_v3_1_start() local
429 rb_bufsz = order_base_2(ring->ring_size); in uvd_v3_1_start()
430 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v3_1_start()
431 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v3_1_start()
H A Diceland_ih.c109 int rb_bufsz; in iceland_ih_irq_init() local
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in iceland_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
H A Dcz_ih.c110 int rb_bufsz; in cz_ih_irq_init() local
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cz_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
H A Dcik_ih.c109 int rb_bufsz; in cik_ih_irq_init() local
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cik_ih_irq_init()
131 (rb_bufsz << 1)); in cik_ih_irq_init()
H A Dtonga_ih.c106 int rb_bufsz; in tonga_ih_irq_init() local
125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in tonga_ih_irq_init()
127 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in tonga_ih_irq_init()
H A Dsi_ih.c65 int rb_bufsz; in si_ih_irq_init() local
77 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in si_ih_irq_init()
81 (rb_bufsz << 1) | in si_ih_irq_init()
H A Dvcn_v2_5.c775 uint32_t rb_bufsz, tmp; in vcn_v2_5_start_dpg_mode() local
871 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_start_dpg_mode()
872 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start_dpg_mode()
918 uint32_t rb_bufsz, tmp; in vcn_v2_5_start() local
1063 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_start()
1064 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start()
1167 uint32_t offset, size, tmp, i, rb_bufsz; in vcn_v2_5_sriov_start() local
1282 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_sriov_start()
1283 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_sriov_start()
H A Duvd_v5_0.c293 uint32_t rb_bufsz, tmp; in uvd_v5_0_start() local
390 rb_bufsz = order_base_2(ring->ring_size); in uvd_v5_0_start()
392 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in uvd_v5_0_start()
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Duvd_v1_0.c266 uint32_t rb_bufsz; in uvd_v1_0_start() local
377 rb_bufsz = order_base_2(ring->ring_size); in uvd_v1_0_start()
378 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v1_0_start()
379 WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v1_0_start()
H A Dni_dma.c191 u32 rb_bufsz; in cayman_dma_resume() local
210 rb_bufsz = order_base_2(ring->ring_size / 4); in cayman_dma_resume()
211 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
H A Dr600_dma.c124 u32 rb_bufsz; in r600_dma_resume() local
131 rb_bufsz = order_base_2(ring->ring_size / 4); in r600_dma_resume()
132 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Duvd_v1_0.c266 uint32_t rb_bufsz; in uvd_v1_0_start() local
377 rb_bufsz = order_base_2(ring->ring_size); in uvd_v1_0_start()
378 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v1_0_start()
379 WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v1_0_start()
H A Dr600_dma.c123 u32 rb_bufsz; in r600_dma_resume() local
130 rb_bufsz = order_base_2(ring->ring_size / 4); in r600_dma_resume()
131 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
H A Dni_dma.c190 u32 rb_bufsz; in cayman_dma_resume() local
209 rb_bufsz = order_base_2(ring->ring_size / 4); in cayman_dma_resume()
210 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ih.c44 u32 rb_bufsz; in amdgpu_ih_ring_init() local
48 rb_bufsz = order_base_2(ring_size / 4); in amdgpu_ih_ring_init()
49 ring_size = (1 << rb_bufsz) * 4; in amdgpu_ih_ring_init()
H A Diceland_ih.c109 int rb_bufsz; in iceland_ih_irq_init() local
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in iceland_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
H A Dcik_ih.c109 int rb_bufsz; in cik_ih_irq_init() local
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cik_ih_irq_init()
131 (rb_bufsz << 1)); in cik_ih_irq_init()
H A Dcz_ih.c110 int rb_bufsz; in cz_ih_irq_init() local
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cz_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
H A Dsi_ih.c65 int rb_bufsz; in si_ih_irq_init() local
77 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in si_ih_irq_init()
81 (rb_bufsz << 1) | in si_ih_irq_init()
H A Dtonga_ih.c106 int rb_bufsz; in tonga_ih_irq_init() local
125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in tonga_ih_irq_init()
127 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in tonga_ih_irq_init()
H A Duvd_v4_2.c281 uint32_t rb_bufsz; in uvd_v4_2_start() local
391 rb_bufsz = order_base_2(ring->ring_size); in uvd_v4_2_start()
392 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v4_2_start()
393 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v4_2_start()
H A Duvd_v3_1.c323 uint32_t rb_bufsz; in uvd_v3_1_start() local
433 rb_bufsz = order_base_2(ring->ring_size); in uvd_v3_1_start()
434 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v3_1_start()
435 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v3_1_start()
H A Dvcn_v2_5.c823 uint32_t rb_bufsz, tmp; in vcn_v2_5_start_dpg_mode() local
919 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_start_dpg_mode()
920 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start_dpg_mode()
966 uint32_t rb_bufsz, tmp; in vcn_v2_5_start() local
1111 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_start()
1112 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start()
1215 uint32_t offset, size, tmp, i, rb_bufsz; in vcn_v2_5_sriov_start() local
1330 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_sriov_start()
1331 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_sriov_start()

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