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Searched refs:pre_div (Results 1 - 25 of 89) sorted by relevance

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/kernel/linux/linux-5.10/drivers/pwm/
H A Dpwm-meson.c91 u8 pre_div; member
166 unsigned int pre_div, cnt, duty_cnt; in meson_pwm_calc() local
190 pre_div = div64_u64(fin_freq * period, NSEC_PER_SEC * 0xffffLL); in meson_pwm_calc()
191 if (pre_div > MISC_CLK_DIV_MASK) { in meson_pwm_calc()
192 dev_err(meson->chip.dev, "unable to get period pre_div\n"); in meson_pwm_calc()
196 cnt = div64_u64(fin_freq * period, NSEC_PER_SEC * (pre_div + 1)); in meson_pwm_calc()
202 dev_dbg(meson->chip.dev, "period=%llu pre_div=%u cnt=%u\n", period, in meson_pwm_calc()
203 pre_div, cnt); in meson_pwm_calc()
206 channel->pre_div = pre_div; in meson_pwm_calc()
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/kernel/linux/linux-5.10/drivers/clk/sunxi/
H A Dclk-sun9i-cpus.c75 u8 div, pre_div = 1; in sun9i_a80_cpus_clk_round() local
90 pre_div = div; in sun9i_a80_cpus_clk_round()
93 pre_div = DIV_ROUND_UP(div, 2); in sun9i_a80_cpus_clk_round()
96 pre_div = DIV_ROUND_UP(div, 3); in sun9i_a80_cpus_clk_round()
99 pre_div = DIV_ROUND_UP(div, 4); in sun9i_a80_cpus_clk_round()
107 *pre_divp = pre_div - 1; in sun9i_a80_cpus_clk_round()
110 return parent_rate / pre_div / div; in sun9i_a80_cpus_clk_round()
157 u8 div, pre_div, parent; in sun9i_a80_cpus_clk_set_rate() local
166 sun9i_a80_cpus_clk_round(rate, &div, &pre_div, parent, parent_rate); in sun9i_a80_cpus_clk_set_rate()
169 reg = SUN9I_CPUS_PLL4_DIV_SET(reg, pre_div); in sun9i_a80_cpus_clk_set_rate()
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/kernel/linux/linux-6.6/drivers/clk/sunxi/
H A Dclk-sun9i-cpus.c75 u8 div, pre_div = 1; in sun9i_a80_cpus_clk_round() local
90 pre_div = div; in sun9i_a80_cpus_clk_round()
93 pre_div = DIV_ROUND_UP(div, 2); in sun9i_a80_cpus_clk_round()
96 pre_div = DIV_ROUND_UP(div, 3); in sun9i_a80_cpus_clk_round()
99 pre_div = DIV_ROUND_UP(div, 4); in sun9i_a80_cpus_clk_round()
107 *pre_divp = pre_div - 1; in sun9i_a80_cpus_clk_round()
110 return parent_rate / pre_div / div; in sun9i_a80_cpus_clk_round()
157 u8 div, pre_div, parent; in sun9i_a80_cpus_clk_set_rate() local
166 sun9i_a80_cpus_clk_round(rate, &div, &pre_div, parent, parent_rate); in sun9i_a80_cpus_clk_set_rate()
169 reg = SUN9I_CPUS_PLL4_DIV_SET(reg, pre_div); in sun9i_a80_cpus_clk_set_rate()
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/kernel/linux/linux-5.10/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi_ddc_clk.c18 u8 pre_div; member
29 const u8 pre_div, in sun4i_ddc_calc_divider()
40 tmp_rate = (((parent_rate / pre_div) / 10) >> _n) / in sun4i_ddc_calc_divider()
67 return sun4i_ddc_calc_divider(rate, *prate, ddc->pre_div, in sun4i_ddc_round_rate()
82 return (((parent_rate / ddc->pre_div) / 10) >> n) / in sun4i_ddc_recalc_rate()
92 sun4i_ddc_calc_divider(rate, parent_rate, ddc->pre_div, in sun4i_ddc_set_rate()
134 ddc->pre_div = hdmi->variant->ddc_clk_pre_divider; in sun4i_ddc_create()
27 sun4i_ddc_calc_divider(unsigned long rate, unsigned long parent_rate, const u8 pre_div, const u8 m_offset, u8 *m, u8 *n) sun4i_ddc_calc_divider() argument
/kernel/linux/linux-6.6/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi_ddc_clk.c18 u8 pre_div; member
29 const u8 pre_div, in sun4i_ddc_calc_divider()
40 tmp_rate = (((parent_rate / pre_div) / 10) >> _n) / in sun4i_ddc_calc_divider()
67 return sun4i_ddc_calc_divider(rate, *prate, ddc->pre_div, in sun4i_ddc_round_rate()
82 return (((parent_rate / ddc->pre_div) / 10) >> n) / in sun4i_ddc_recalc_rate()
92 sun4i_ddc_calc_divider(rate, parent_rate, ddc->pre_div, in sun4i_ddc_set_rate()
134 ddc->pre_div = hdmi->variant->ddc_clk_pre_divider; in sun4i_ddc_create()
27 sun4i_ddc_calc_divider(unsigned long rate, unsigned long parent_rate, const u8 pre_div, const u8 m_offset, u8 *m, u8 *n) sun4i_ddc_calc_divider() argument
/kernel/linux/linux-5.10/drivers/clk/bcm/
H A Dclk-kona-setup.c72 div = &peri->pre_div; in clk_requires_trigger()
138 div = &peri->pre_div; in peri_clk_data_offsets_valid()
372 struct bcm_clk_div *pre_div; in kona_dividers_valid() local
377 if (!divider_exists(&peri->div) || !divider_exists(&peri->pre_div)) in kona_dividers_valid()
381 pre_div = &peri->pre_div; in kona_dividers_valid()
382 if (divider_is_fixed(div) || divider_is_fixed(pre_div)) in kona_dividers_valid()
387 return div->u.s.frac_width + pre_div->u.s.frac_width <= limit; in kona_dividers_valid()
408 struct bcm_clk_div *pre_div; in peri_clk_data_valid() local
450 pre_div in peri_clk_data_valid()
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H A Dclk-kona.c694 struct bcm_clk_div *div, struct bcm_clk_div *pre_div, in clk_recalc_rate()
716 if (pre_div && divider_exists(pre_div)) { in clk_recalc_rate()
719 scaled_rate = scale_rate(pre_div, parent_rate); in clk_recalc_rate()
721 scaled_div = divider_read_scaled(ccu, pre_div); in clk_recalc_rate()
749 struct bcm_clk_div *pre_div, in round_rate()
774 if (divider_exists(pre_div)) { in round_rate()
778 scaled_rate = scale_rate(pre_div, parent_rate); in round_rate()
780 scaled_pre_div = divider_read_scaled(ccu, pre_div); in round_rate()
1004 return clk_recalc_rate(bcm_clk->ccu, &data->div, &data->pre_div, in kona_peri_clk_recalc_rate()
693 clk_recalc_rate(struct ccu_data *ccu, struct bcm_clk_div *div, struct bcm_clk_div *pre_div, unsigned long parent_rate) clk_recalc_rate() argument
748 round_rate(struct ccu_data *ccu, struct bcm_clk_div *div, struct bcm_clk_div *pre_div, unsigned long rate, unsigned long parent_rate, u64 *scaled_div) round_rate() argument
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/kernel/linux/linux-6.6/drivers/clk/bcm/
H A Dclk-kona-setup.c64 div = &peri->pre_div; in clk_requires_trigger()
130 div = &peri->pre_div; in peri_clk_data_offsets_valid()
364 struct bcm_clk_div *pre_div; in kona_dividers_valid() local
369 if (!divider_exists(&peri->div) || !divider_exists(&peri->pre_div)) in kona_dividers_valid()
373 pre_div = &peri->pre_div; in kona_dividers_valid()
374 if (divider_is_fixed(div) || divider_is_fixed(pre_div)) in kona_dividers_valid()
379 return div->u.s.frac_width + pre_div->u.s.frac_width <= limit; in kona_dividers_valid()
400 struct bcm_clk_div *pre_div; in peri_clk_data_valid() local
442 pre_div in peri_clk_data_valid()
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H A Dclk-kona.c686 struct bcm_clk_div *div, struct bcm_clk_div *pre_div, in clk_recalc_rate()
708 if (pre_div && divider_exists(pre_div)) { in clk_recalc_rate()
711 scaled_rate = scale_rate(pre_div, parent_rate); in clk_recalc_rate()
713 scaled_div = divider_read_scaled(ccu, pre_div); in clk_recalc_rate()
741 struct bcm_clk_div *pre_div, in round_rate()
766 if (divider_exists(pre_div)) { in round_rate()
770 scaled_rate = scale_rate(pre_div, parent_rate); in round_rate()
772 scaled_pre_div = divider_read_scaled(ccu, pre_div); in round_rate()
996 return clk_recalc_rate(bcm_clk->ccu, &data->div, &data->pre_div, in kona_peri_clk_recalc_rate()
685 clk_recalc_rate(struct ccu_data *ccu, struct bcm_clk_div *div, struct bcm_clk_div *pre_div, unsigned long parent_rate) clk_recalc_rate() argument
740 round_rate(struct ccu_data *ccu, struct bcm_clk_div *div, struct bcm_clk_div *pre_div, unsigned long rate, unsigned long parent_rate, u64 *scaled_div) round_rate() argument
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/kernel/linux/linux-5.10/drivers/clk/qcom/
H A Dclk-rcg.h15 u8 pre_div; member
43 * struct pre_div - pre-divider
47 struct pre_div { struct
80 struct pre_div p;
118 struct pre_div p[2];
H A Dclk-rcg.c113 static u32 ns_to_pre_div(struct pre_div *p, u32 ns) in ns_to_pre_div()
120 static u32 pre_div_to_ns(struct pre_div *p, u8 pre_div, u32 ns) in pre_div_to_ns() argument
128 ns |= pre_div << p->pre_div_shift; in pre_div_to_ns()
203 struct pre_div *p; in configure_bank()
267 ns = pre_div_to_ns(p, f->pre_div - 1, ns); in configure_bank()
312 f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1; in clk_dyn_rcg_set_parent()
323 * pre_div n
326 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 pre_div) in calc_rate() argument
328 if (pre_div) in calc_rate()
345 u32 pre_div, m = 0, n = 0, ns, md, mode = 0; clk_rcg_recalc_rate() local
370 u32 m, n, pre_div, ns, md, mode, reg; clk_dyn_rcg_recalc_rate() local
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H A Dclk-rcg2.c220 if (f->pre_div) { in _freq_tbl_determine_rate()
224 rate *= f->pre_div + 1; in _freq_tbl_determine_rate()
297 cfg = f->pre_div << CFG_SRC_DIV_SHIFT; in __clk_rcg2_configure()
439 f.pre_div = hid_div; in clk_edp_pixel_set_rate()
440 f.pre_div >>= CFG_SRC_DIV_SHIFT; in clk_edp_pixel_set_rate()
441 f.pre_div &= mask; in clk_edp_pixel_set_rate()
547 f.pre_div = div; in clk_byte_set_rate()
606 f.pre_div = div; in clk_byte2_set_rate()
703 f.pre_div = hid_div; in clk_pixel_set_rate()
704 f.pre_div >> in clk_pixel_set_rate()
1044 u32 level, mask, cfg, m = 0, n = 0, mode, pre_div; clk_rcg2_dfs_recalc_rate() local
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/kernel/linux/linux-6.6/drivers/clk/qcom/
H A Dclk-rcg.h15 u8 pre_div; member
43 * struct pre_div - pre-divider
47 struct pre_div { struct
80 struct pre_div p;
119 struct pre_div p[2];
H A Dclk-rcg.c113 static u32 ns_to_pre_div(struct pre_div *p, u32 ns) in ns_to_pre_div()
120 static u32 pre_div_to_ns(struct pre_div *p, u8 pre_div, u32 ns) in pre_div_to_ns() argument
128 ns |= pre_div << p->pre_div_shift; in pre_div_to_ns()
203 struct pre_div *p; in configure_bank()
267 ns = pre_div_to_ns(p, f->pre_div - 1, ns); in configure_bank()
312 f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1; in clk_dyn_rcg_set_parent()
323 * pre_div n
326 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 pre_div) in calc_rate() argument
328 if (pre_div) in calc_rate()
345 u32 pre_div, m = 0, n = 0, ns, md, mode = 0; clk_rcg_recalc_rate() local
370 u32 m, n, pre_div, ns, md, mode, reg; clk_dyn_rcg_recalc_rate() local
[all...]
H A Dclk-rcg2.c240 if (f->pre_div) { in _freq_tbl_determine_rate()
244 rate *= f->pre_div + 1; in _freq_tbl_determine_rate()
318 cfg = f->pre_div << CFG_SRC_DIV_SHIFT; in __clk_rcg2_configure()
569 f.pre_div = hid_div; in clk_edp_pixel_set_rate()
570 f.pre_div >>= CFG_SRC_DIV_SHIFT; in clk_edp_pixel_set_rate()
571 f.pre_div &= mask; in clk_edp_pixel_set_rate()
677 f.pre_div = div; in clk_byte_set_rate()
736 f.pre_div = div; in clk_byte2_set_rate()
833 f.pre_div = hid_div; in clk_pixel_set_rate()
834 f.pre_div >> in clk_pixel_set_rate()
1241 u32 level, mask, cfg, m = 0, n = 0, mode, pre_div; clk_rcg2_dfs_recalc_rate() local
[all...]
/kernel/linux/linux-5.10/drivers/clk/
H A Dclk-sparx5.c53 u8 pre_div; member
65 int divt = sel_rates[conf->rot_sel] * (1 + conf->pre_div); in s5_calc_freq()
91 conf->pre_div = i; in s5_search_fractional()
183 val |= FIELD_PREP(PLL_PRE_DIV, conf.pre_div); in s5_pll_set_rate()
203 conf.pre_div = FIELD_GET(PLL_PRE_DIV, val); in s5_pll_recalc_rate()
/kernel/linux/linux-5.10/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt8173.c160 unsigned int pre_div; in mtk_hdmi_pll_set_rate() local
170 pre_div = 0; in mtk_hdmi_pll_set_rate()
173 pre_div = 1; in mtk_hdmi_pll_set_rate()
176 pre_div = 1; in mtk_hdmi_pll_set_rate()
181 (pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV); in mtk_hdmi_pll_set_rate()
/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-sparx5.c53 u8 pre_div; member
65 int divt = sel_rates[conf->rot_sel] * (1 + conf->pre_div); in s5_calc_freq()
91 conf->pre_div = i; in s5_search_fractional()
183 val |= FIELD_PREP(PLL_PRE_DIV, conf.pre_div); in s5_pll_set_rate()
203 conf.pre_div = FIELD_GET(PLL_PRE_DIV, val); in s5_pll_recalc_rate()
/kernel/linux/linux-6.6/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt8173.c140 unsigned int pre_div; in mtk_hdmi_pll_set_rate() local
150 pre_div = 0; in mtk_hdmi_pll_set_rate()
153 pre_div = 1; in mtk_hdmi_pll_set_rate()
156 pre_div = 1; in mtk_hdmi_pll_set_rate()
160 mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_PLL_PREDIV, pre_div); in mtk_hdmi_pll_set_rate()
/kernel/linux/linux-5.10/sound/soc/codecs/
H A Drt1016.c310 int pre_div, bclk_ms, frame_size; in rt1016_hw_params() local
314 pre_div = rl6231_get_clk_info(rt1016->sysclk, rt1016->lrck); in rt1016_hw_params()
315 if (pre_div < 0) { in rt1016_hw_params()
334 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt1016_hw_params()
335 rt1016->lrck, pre_div, dai->id); in rt1016_hw_params()
358 ((pre_div + 3) << RT1016_FS_PD_SFT) | in rt1016_hw_params()
359 (pre_div << RT1016_OSR_PD_SFT)); in rt1016_hw_params()
H A Drt1308.c459 int pre_div, bclk_ms, frame_size; in rt1308_hw_params() local
462 pre_div = rt1308_get_clk_info(rt1308->sysclk, rt1308->lrck); in rt1308_hw_params()
463 if (pre_div < 0) { in rt1308_hw_params()
479 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", in rt1308_hw_params()
480 bclk_ms, pre_div, dai->id); in rt1308_hw_params()
482 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt1308_hw_params()
483 rt1308->lrck, pre_div, dai->id); in rt1308_hw_params()
505 val_clk = pre_div << RT1308_DIV_FS_SYS_SFT; in rt1308_hw_params()
/kernel/linux/linux-6.6/sound/soc/codecs/
H A Drt1016.c309 int pre_div, bclk_ms, frame_size; in rt1016_hw_params() local
313 pre_div = rl6231_get_clk_info(rt1016->sysclk, rt1016->lrck); in rt1016_hw_params()
314 if (pre_div < 0) { in rt1016_hw_params()
333 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n", in rt1016_hw_params()
334 rt1016->lrck, pre_div, dai->id); in rt1016_hw_params()
357 ((pre_div + 3) << RT1016_FS_PD_SFT) | in rt1016_hw_params()
358 (pre_div << RT1016_OSR_PD_SFT)); in rt1016_hw_params()
H A Drt1019.c161 int pre_div, bclk_ms, frame_size; in rt1019_hw_params() local
167 pre_div = rl6231_get_clk_info(rt1019->sysclk, rt1019->lrck); in rt1019_hw_params()
168 if (pre_div < 0) { in rt1019_hw_params()
184 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", in rt1019_hw_params()
185 bclk_ms, pre_div, dai->id); in rt1019_hw_params()
187 switch (pre_div) { in rt1019_hw_params()
/kernel/linux/linux-5.10/drivers/mmc/host/
H A Dsdhci-of-esdhc.c646 unsigned int pre_div = 1, div = 1; in esdhc_of_set_clock() local
657 /* Start pre_div at 2 for vendor version < 2.3. */ in esdhc_of_set_clock()
659 pre_div = 2; in esdhc_of_set_clock()
671 /* Calculate pre_div and div. */ in esdhc_of_set_clock()
672 while (host->max_clk / pre_div / 16 > clock_fixup && pre_div < 256) in esdhc_of_set_clock()
673 pre_div *= 2; in esdhc_of_set_clock()
675 while (host->max_clk / pre_div / div > clock_fixup && div < 16) in esdhc_of_set_clock()
678 esdhc->div_ratio = pre_div * div; in esdhc_of_set_clock()
686 pre_div in esdhc_of_set_clock()
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/kernel/linux/linux-6.6/drivers/mmc/host/
H A Dsdhci-of-esdhc.c653 unsigned int pre_div = 1, div = 1; in esdhc_of_set_clock() local
664 /* Start pre_div at 2 for vendor version < 2.3. */ in esdhc_of_set_clock()
666 pre_div = 2; in esdhc_of_set_clock()
678 /* Calculate pre_div and div. */ in esdhc_of_set_clock()
679 while (host->max_clk / pre_div / 16 > clock_fixup && pre_div < 256) in esdhc_of_set_clock()
680 pre_div *= 2; in esdhc_of_set_clock()
682 while (host->max_clk / pre_div / div > clock_fixup && div < 16) in esdhc_of_set_clock()
685 esdhc->div_ratio = pre_div * div; in esdhc_of_set_clock()
693 pre_div in esdhc_of_set_clock()
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