Lines Matching refs:pre_div
75 u8 div, pre_div = 1;
90 pre_div = div;
93 pre_div = DIV_ROUND_UP(div, 2);
96 pre_div = DIV_ROUND_UP(div, 3);
99 pre_div = DIV_ROUND_UP(div, 4);
107 *pre_divp = pre_div - 1;
110 return parent_rate / pre_div / div;
157 u8 div, pre_div, parent;
166 sun9i_a80_cpus_clk_round(rate, &div, &pre_div, parent, parent_rate);
169 reg = SUN9I_CPUS_PLL4_DIV_SET(reg, pre_div);