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Searched refs:pll0 (Results 1 - 20 of 20) sorted by relevance

/kernel/linux/linux-5.10/drivers/bcma/
H A Ddriver_chipcommon_pmu.c84 u32 pll0, mask; in bcma_pmu2_pll_init0() local
115 pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); in bcma_pmu2_pll_init0()
116 freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> in bcma_pmu2_pll_init0()
137 pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; in bcma_pmu2_pll_init0()
138 pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; in bcma_pmu2_pll_init0()
139 bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); in bcma_pmu2_pll_init0()
351 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
353 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) in bcma_pmu_pll_clock() argument
358 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL in bcma_pmu_pll_clock()
389 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m) bcma_pmu_pll_clock_bcm4706() argument
[all...]
/kernel/linux/linux-6.6/drivers/bcma/
H A Ddriver_chipcommon_pmu.c84 u32 pll0, mask; in bcma_pmu2_pll_init0() local
115 pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0); in bcma_pmu2_pll_init0()
116 freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >> in bcma_pmu2_pll_init0()
137 pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK; in bcma_pmu2_pll_init0()
138 pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT; in bcma_pmu2_pll_init0()
139 bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0); in bcma_pmu2_pll_init0()
351 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
353 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) in bcma_pmu_pll_clock() argument
358 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL in bcma_pmu_pll_clock()
389 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m) bcma_pmu_pll_clock_bcm4706() argument
[all...]
/kernel/linux/linux-5.10/drivers/soc/kendryte/
H A Dk210-sysctl.c136 u32 clksel0, pll0; in k210_sysctl_clk_recalc_rate() local
151 pll0 = readl(s->regs + K210_SYSCTL_PLL0); in k210_sysctl_clk_recalc_rate()
152 clkr0 = 1 + FIELD_GET(GENMASK(3, 0), pll0); in k210_sysctl_clk_recalc_rate()
153 clkf0 = 1 + FIELD_GET(GENMASK(9, 4), pll0); in k210_sysctl_clk_recalc_rate()
154 clkod0 = 1 + FIELD_GET(GENMASK(13, 10), pll0); in k210_sysctl_clk_recalc_rate()
/kernel/linux/linux-5.10/drivers/gpu/drm/tegra/
H A Dhdmi.c36 u32 pll0; member
129 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
144 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
162 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
176 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
190 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
208 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
226 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
245 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
264 .pll0
[all...]
H A Dsor.c365 unsigned int pll0; member
1456 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1458 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
2296 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2299 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2494 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2501 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2779 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2781 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2820 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/tegra/
H A Dhdmi.c42 u32 pll0; member
138 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
153 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
171 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
185 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
199 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
217 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
235 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
254 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
273 .pll0
[all...]
H A Dsor.c365 unsigned int pll0; member
1457 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1459 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
2292 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2295 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2490 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2497 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2775 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2777 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2816 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
[all...]
/kernel/linux/linux-5.10/drivers/clk/mxs/
H A Dclk-imx28.c127 static const char *const sel_pll0[] __initconst = { "pll0", "ref_xtal", };
130 static const char *const ptp_sels[] __initconst = { "ref_xtal", "pll0", };
133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
171 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); in mx28_clocks_init()
172 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); in mx28_clocks_init()
173 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); in mx28_clocks_init()
174 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); in mx28_clocks_init()
175 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC in mx28_clocks_init()
[all...]
/kernel/linux/linux-6.6/drivers/clk/mxs/
H A Dclk-imx28.c127 static const char *const sel_pll0[] __initconst = { "pll0", "ref_xtal", };
130 static const char *const ptp_sels[] __initconst = { "ref_xtal", "pll0", };
133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
171 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); in mx28_clocks_init()
172 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); in mx28_clocks_init()
173 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); in mx28_clocks_init()
174 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); in mx28_clocks_init()
175 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC in mx28_clocks_init()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h207 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
H A Dintel_dpll_mgr.c1950 PORT_PLL_M2_INT_MASK, pll->state.hw_state.pll0); in bxt_ddi_pll_enable()
2067 hw_state->pll0 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0)); in bxt_ddi_pll_get_hw_state()
2068 hw_state->pll0 &= PORT_PLL_M2_INT_MASK; in bxt_ddi_pll_get_hw_state()
2211 dpll_hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2 >> 22); in bxt_ddi_set_dpll_hw_state()
2243 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, pll_state->pll0) << 22; in bxt_ddi_pll_get_freq()
2333 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " in bxt_dump_hw_state()
2337 hw_state->pll0, in bxt_dump_hw_state()
H A Dintel_display.c5329 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); in intel_pipe_config_compare()
/kernel/linux/linux-5.10/arch/arm/mach-davinci/
H A Dda850.c650 void __iomem *pll0; in da850_init_time() local
657 pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K); in da850_init_time()
660 da850_pll0_init(NULL, pll0, cfgchip); in da850_init_time()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h195 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
H A Dintel_dpll_mgr.c1859 temp |= pll->state.hw_state.pll0; in bxt_ddi_pll_enable()
1993 hw_state->pll0 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0)); in bxt_ddi_pll_get_hw_state()
1994 hw_state->pll0 &= PORT_PLL_M2_MASK; in bxt_ddi_pll_get_hw_state()
2162 dpll_hw_state->pll0 = clk_div->m2_int; in bxt_ddi_set_dpll_hw_state()
2214 clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22; in bxt_ddi_pll_get_freq()
2268 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " in bxt_dump_hw_state()
2272 hw_state->pll0, in bxt_dump_hw_state()
H A Dintel_display.c14001 PIPE_CONF_CHECK_X(dpll_hw_state.pll0); in intel_pipe_config_compare()
/kernel/linux/linux-6.6/drivers/clk/qcom/
H A Dgcc-mdm9615.c47 static struct clk_pll pll0 = { variable
56 .name = "pll0",
69 &pll0.clkr.hw,
1615 [PLL0] = &pll0.clkr,
H A Dgcc-ipq806x.c32 static struct clk_pll pll0 = { variable
41 .name = "pll0",
54 &pll0.clkr.hw,
3067 [PLL0] = &pll0.clkr,
/kernel/linux/linux-5.10/drivers/clk/qcom/
H A Dgcc-mdm9615.c40 static struct clk_pll pll0 = { variable
49 .name = "pll0",
61 .parent_names = (const char *[]){ "pll0" },
1589 [PLL0] = &pll0.clkr,
H A Dgcc-ipq806x.c28 static struct clk_pll pll0 = { variable
37 .name = "pll0",
49 .parent_names = (const char *[]){ "pll0" },
2756 [PLL0] = &pll0.clkr,

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