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Searched refs:pcw_chg_reg (Results 1 - 14 of 14) sorted by relevance

/kernel/linux/linux-6.6/drivers/clk/mediatek/
H A Dclk-pll.h46 u32 pcw_chg_reg; member
H A Dclk-mt8195-apusys_pll.c22 * The "en_reg" and "pcw_chg_reg" fields are standard offset register compared
47 .pcw_chg_reg = 0, \
H A Dclk-mt8188-apmixedsys.c55 .pcw_chg_reg = _pcw_chg_reg, \
H A Dclk-pll.c298 if (data->pcw_chg_reg) in mtk_clk_register_pll_ops()
299 pll->pcw_chg_addr = base + data->pcw_chg_reg; in mtk_clk_register_pll_ops()
H A Dclk-mt8183-apmixedsys.c77 .pcw_chg_reg = _pcw_chg_reg, \
H A Dclk-mt8192-apmixedsys.c58 .pcw_chg_reg = _pcw_chg_reg, \
H A Dclk-mt8365-apmixedsys.c41 .pcw_chg_reg = _pcw_chg_reg, \
H A Dclk-mt8186-apmixedsys.c41 .pcw_chg_reg = 0, \
H A Dclk-mt8195-apmixedsys.c56 .pcw_chg_reg = _pcw_chg_reg, \
H A Dclk-mt6779.c1168 .pcw_chg_reg = _pcw_chg_reg, \
/kernel/linux/linux-5.10/drivers/clk/mediatek/
H A Dclk-pll.c316 if (data->pcw_chg_reg) in mtk_clk_register_pll()
317 pll->pcw_chg_addr = base + data->pcw_chg_reg; in mtk_clk_register_pll()
H A Dclk-mtk.h233 uint32_t pcw_chg_reg; member
H A Dclk-mt8183.c1090 .pcw_chg_reg = _pcw_chg_reg, \
H A Dclk-mt6779.c1167 .pcw_chg_reg = _pcw_chg_reg, \

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