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Help
Searched
refs:nv04_display
(Results
1 - 22
of
22
) sorted by relevance
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv04/
H
A
D
disp.c
60
struct
nv04_display
*disp =
nv04_display
(dev);
in nv04_display_fini()
101
struct
nv04_display
*disp =
nv04_display
(dev);
in nv04_display_init()
191
struct
nv04_display
*disp =
nv04_display
(dev);
in nv04_display_destroy()
223
struct
nv04_display
*disp;
in nv04_display_create()
H
A
D
dfp.c
95
struct nv04_crtc_reg *crtcstate =
nv04_display
(dev)->mode_reg.crtc_reg;
in nv04_dfp_disable()
122
fpc = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
in nv04_dfp_update_fp_control()
137
fpc = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
in nv04_dfp_update_fp_control()
207
struct nv04_mode_state *state = &
nv04_display
(dev)->mode_reg;
in nv04_dfp_prepare_sel_clk()
237
if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS &&
nv04_display
(dev)->saved_reg.sel_clk & 0xf0) {
in nv04_dfp_prepare_sel_clk()
238
int shift = (
nv04_display
(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1;
in nv04_dfp_prepare_sel_clk()
251
struct nv04_crtc_reg *crtcstate =
nv04_display
(dev)->mode_reg.crtc_reg;
in nv04_dfp_prepare()
288
struct nv04_crtc_reg *regp = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index];
in nv04_dfp_mode_set()
289
struct nv04_crtc_reg *savep = &
nv04_display
(dev)->saved_reg.crtc_reg[nv_crtc->index];
in nv04_dfp_mode_set()
464
nv04_display
(de
in nv04_dfp_commit()
[all...]
H
A
D
crtc.c
67
struct nv04_crtc_reg *regp = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index];
in nv_crtc_set_digital_vibrance()
82
struct nv04_crtc_reg *regp = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index];
in nv_crtc_set_image_sharpening()
124
struct nv04_mode_state *state = &
nv04_display
(dev)->mode_reg;
in nv_crtc_calc_state_ext()
241
struct nv04_crtc_reg *regp = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index];
in nv_crtc_mode_set_vga()
466
struct nv04_crtc_reg *regp = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index];
in nv_crtc_mode_set_regs()
467
struct nv04_crtc_reg *savep = &
nv04_display
(dev)->saved_reg.crtc_reg[nv_crtc->index];
in nv_crtc_mode_set_regs()
546
regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] =
nv04_display
(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
in nv_crtc_mode_set_regs()
612
struct
nv04_display
*disp =
nv04_display
(crtc->dev);
in nv_crtc_swap_fbs()
659
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK,
nv04_display
(de
in nv_crtc_mode_set()
[all...]
H
A
D
disp.h
81
struct
nv04_display
{
struct
90
static inline struct
nv04_display
*
91
nv04_display
(struct drm_device *dev)
in nv04_display()
function
96
/*
nv04_display
.c */
H
A
D
tvnv04.c
79
struct nv04_mode_state *state = &
nv04_display
(dev)->mode_reg;
in nv04_tv_dpms()
107
struct nv04_crtc_reg *state = &
nv04_display
(dev)->mode_reg.crtc_reg[head];
in nv04_tv_bind()
146
struct nv04_crtc_reg *regp = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index];
in nv04_tv_mode_set()
H
A
D
cursor.c
42
struct nv04_crtc_reg *regp = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index];
in nv04_cursor_set_offset()
H
A
D
dac.c
432
uint32_t *dac_users = &
nv04_display
(dev)->dac_users[ffs(dcb->or) - 1];
in nv04_dac_update_dacclk()
457
(
nv04_display
(dev)->dac_users[ffs(dcb->or) - 1] & ~(1 << dcb->index));
in nv04_dac_in_use()
H
A
D
tvnv17.c
403
uint8_t *cr_lcd = &
nv04_display
(dev)->mode_reg.crtc_reg[head].CRTC[
in nv17_tv_prepare()
464
struct nv04_crtc_reg *regs = &
nv04_display
(dev)->mode_reg.crtc_reg[head];
in nv17_tv_mode_set()
H
A
D
hw.h
376
&
nv04_display
(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
in nv_show_cursor()
H
A
D
hw.c
299
nv04_display
(dev)->saved_vga_font[plane][i] =
in nouveau_vga_font_io()
302
iowrite32_native(
nv04_display
(dev)->saved_vga_font[plane][i],
in nouveau_vga_font_io()
H
A
D
tvmodesnv17.c
547
struct nv04_crtc_reg *regs = &
nv04_display
(dev)->mode_reg.crtc_reg[head];
in nv17_ctv_update_rescaler()
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/dispnv04/
H
A
D
disp.c
60
struct
nv04_display
*disp =
nv04_display
(dev);
in nv04_display_fini()
101
struct
nv04_display
*disp =
nv04_display
(dev);
in nv04_display_init()
191
struct
nv04_display
*disp =
nv04_display
(dev);
in nv04_display_destroy()
223
struct
nv04_display
*disp;
in nv04_display_create()
H
A
D
dfp.c
95
struct nv04_crtc_reg *crtcstate =
nv04_display
(dev)->mode_reg.crtc_reg;
in nv04_dfp_disable()
122
fpc = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
in nv04_dfp_update_fp_control()
137
fpc = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
in nv04_dfp_update_fp_control()
207
struct nv04_mode_state *state = &
nv04_display
(dev)->mode_reg;
in nv04_dfp_prepare_sel_clk()
237
if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS &&
nv04_display
(dev)->saved_reg.sel_clk & 0xf0) {
in nv04_dfp_prepare_sel_clk()
238
int shift = (
nv04_display
(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1;
in nv04_dfp_prepare_sel_clk()
251
struct nv04_crtc_reg *crtcstate =
nv04_display
(dev)->mode_reg.crtc_reg;
in nv04_dfp_prepare()
288
struct nv04_crtc_reg *regp = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index];
in nv04_dfp_mode_set()
289
struct nv04_crtc_reg *savep = &
nv04_display
(dev)->saved_reg.crtc_reg[nv_crtc->index];
in nv04_dfp_mode_set()
464
nv04_display
(de
in nv04_dfp_commit()
[all...]
H
A
D
crtc.c
67
struct nv04_crtc_reg *regp = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index];
in nv_crtc_set_digital_vibrance()
82
struct nv04_crtc_reg *regp = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index];
in nv_crtc_set_image_sharpening()
124
struct nv04_mode_state *state = &
nv04_display
(dev)->mode_reg;
in nv_crtc_calc_state_ext()
241
struct nv04_crtc_reg *regp = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index];
in nv_crtc_mode_set_vga()
466
struct nv04_crtc_reg *regp = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index];
in nv_crtc_mode_set_regs()
467
struct nv04_crtc_reg *savep = &
nv04_display
(dev)->saved_reg.crtc_reg[nv_crtc->index];
in nv_crtc_mode_set_regs()
546
regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] =
nv04_display
(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
in nv_crtc_mode_set_regs()
612
struct
nv04_display
*disp =
nv04_display
(crtc->dev);
in nv_crtc_swap_fbs()
659
NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK,
nv04_display
(de
in nv_crtc_mode_set()
[all...]
H
A
D
disp.h
83
struct
nv04_display
{
struct
93
static inline struct
nv04_display
*
94
nv04_display
(struct drm_device *dev)
in nv04_display()
function
99
/*
nv04_display
.c */
H
A
D
tvnv04.c
79
struct nv04_mode_state *state = &
nv04_display
(dev)->mode_reg;
in nv04_tv_dpms()
107
struct nv04_crtc_reg *state = &
nv04_display
(dev)->mode_reg.crtc_reg[head];
in nv04_tv_bind()
146
struct nv04_crtc_reg *regp = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index];
in nv04_tv_mode_set()
H
A
D
cursor.c
42
struct nv04_crtc_reg *regp = &
nv04_display
(dev)->mode_reg.crtc_reg[nv_crtc->index];
in nv04_cursor_set_offset()
H
A
D
dac.c
432
uint32_t *dac_users = &
nv04_display
(dev)->dac_users[ffs(dcb->or) - 1];
in nv04_dac_update_dacclk()
457
(
nv04_display
(dev)->dac_users[ffs(dcb->or) - 1] & ~(1 << dcb->index));
in nv04_dac_in_use()
H
A
D
tvnv17.c
404
uint8_t *cr_lcd = &
nv04_display
(dev)->mode_reg.crtc_reg[head].CRTC[
in nv17_tv_prepare()
465
struct nv04_crtc_reg *regs = &
nv04_display
(dev)->mode_reg.crtc_reg[head];
in nv17_tv_mode_set()
H
A
D
hw.h
376
&
nv04_display
(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
in nv_show_cursor()
H
A
D
hw.c
300
nv04_display
(dev)->saved_vga_font[plane][i] =
in nouveau_vga_font_io()
303
iowrite32_native(
nv04_display
(dev)->saved_vga_font[plane][i],
in nouveau_vga_font_io()
H
A
D
tvmodesnv17.c
546
struct nv04_crtc_reg *regs = &
nv04_display
(dev)->mode_reg.crtc_reg[head];
in nv17_ctv_update_rescaler()
Completed in 20 milliseconds