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Searched refs:num_instances (Results 1 - 25 of 57) sorted by relevance

123

/kernel/linux/linux-6.6/drivers/accel/habanalabs/common/
H A Dsecurity.c283 * @num_instances: number of instances to apply configuration to
292 u32 dcore_offset, u32 num_instances, u32 instance_offset, in hl_init_pb_with_mask()
311 for (j = 0 ; j < num_instances ; j++) { in hl_init_pb_with_mask()
312 int seq = i * num_instances + j; in hl_init_pb_with_mask()
335 * @num_instances: number of instances to apply configuration to
344 u32 num_instances, u32 instance_offset, in hl_init_pb()
349 num_instances, instance_offset, pb_blocks, in hl_init_pb()
363 * @num_instances: number of instances to apply configuration to
372 u32 dcore_offset, u32 num_instances, u32 instance_offset, in hl_init_pb_ranges_with_mask()
395 for (j = 0 ; j < num_instances ; in hl_init_pb_ranges_with_mask()
291 hl_init_pb_with_mask(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size, const u32 *user_regs_array, u32 user_regs_array_size, u64 mask) hl_init_pb_with_mask() argument
343 hl_init_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size, const u32 *user_regs_array, u32 user_regs_array_size) hl_init_pb() argument
371 hl_init_pb_ranges_with_mask(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size, const struct range *user_regs_range_array, u32 user_regs_range_array_size, u64 mask) hl_init_pb_ranges_with_mask() argument
429 hl_init_pb_ranges(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size, const struct range *user_regs_range_array, u32 user_regs_range_array_size) hl_init_pb_ranges() argument
455 hl_init_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size, const u32 *user_regs_array, u32 user_regs_array_size) hl_init_pb_single_dcore() argument
503 hl_init_pb_ranges_single_dcore(struct hl_device *hdev, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size, const struct range *user_regs_range_array, u32 user_regs_range_array_size) hl_init_pb_ranges_single_dcore() argument
547 hl_ack_pb_with_mask(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size, u64 mask) hl_ack_pb_with_mask() argument
581 hl_ack_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size) hl_ack_pb() argument
602 hl_ack_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset, u32 num_instances, u32 instance_offset, const u32 pb_blocks[], u32 blocks_array_size) hl_ack_pb_single_dcore() argument
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/kernel/linux/linux-6.6/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-nvidia.c37 unsigned int num_instances; member
69 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_write_reg()
90 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_write_reg64()
112 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_tlb_sync()
137 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_reset()
182 for (inst = 0; inst < nvidia->num_instances; inst++) { in nvidia_smmu_global_fault()
232 for (inst = 0; inst < nvidia->num_instances; inst++) { in nvidia_smmu_context_fault()
325 nvidia_smmu->num_instances++; in nvidia_smmu_impl_init()
336 nvidia_smmu->num_instances++; in nvidia_smmu_impl_init()
339 if (nvidia_smmu->num_instances in nvidia_smmu_impl_init()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_sdma.c42 for (i = 0; i < adev->sdma.num_instances; i++) in amdgpu_sdma_get_instance_from_ring()
55 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_get_index_from_ring()
108 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_ras_late_init()
192 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_destroy_inst_ctx()
236 for (i = 1; i < adev->sdma.num_instances; i++) in amdgpu_sdma_init_microcode()
248 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_init_microcode()
297 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_unset_buffer_funcs_helper()
H A Dsdma_v3_0.c254 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v3_0_free_microcode()
306 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_init_microcode()
331 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v3_0_init_microcode()
518 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_gfx_stop()
577 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_ctx_switch_enable()
619 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_enable()
646 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_gfx_resume()
744 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_gfx_resume()
1093 adev->sdma.num_instances = 1; in sdma_v3_0_early_init()
1096 adev->sdma.num_instances in sdma_v3_0_early_init()
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H A Dsdma_v4_0.c555 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_setup_ulv()
580 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_init_microcode()
880 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_gfx_enable()
916 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_page_stop()
965 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_ctx_switch_enable()
1010 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_enable()
1303 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_load_microcode()
1359 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_start()
1389 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_start()
1767 for (i = 0; i < adev->sdma.num_instances; in sdma_v4_0_sw_init()
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H A Dsdma_v4_4_2.c105 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_inst_init_golden_registers()
134 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_init_microcode()
1341 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_sw_init()
1398 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_sw_fini()
1418 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); in sdma_v4_4_2_hw_init()
1436 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); in sdma_v4_4_2_hw_fini()
1438 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_hw_fini()
1475 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_is_idle()
1492 for (j = 0; j < adev->sdma.num_instances; j++) { in sdma_v4_4_2_wait_for_idle()
1497 if (j == adev->sdma.num_instances) in sdma_v4_4_2_wait_for_idle()
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H A Dcik_sdma.c77 for (i = 0; i < adev->sdma.num_instances; i++) in cik_sdma_free_microcode()
134 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_init_microcode()
146 for (i = 0; i < adev->sdma.num_instances; i++) in cik_sdma_init_microcode()
313 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_gfx_stop()
370 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_ctx_switch_enable()
408 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_enable()
433 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_gfx_resume()
496 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_gfx_resume()
541 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_load_microcode()
929 adev->sdma.num_instances in cik_sdma_early_init()
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H A Dsi_dma.c120 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_stop()
135 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_start()
469 adev->sdma.num_instances = 2; in si_dma_early_init()
497 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_sw_init()
519 for (i = 0; i < adev->sdma.num_instances; i++) in si_dma_sw_fini()
653 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_set_clockgating_state()
665 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_set_clockgating_state()
747 for (i = 0; i < adev->sdma.num_instances; i++) in si_dma_set_ring_funcs()
841 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_set_vm_pte_funcs()
845 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in si_dma_set_vm_pte_funcs()
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H A Dsdma_v2_4.c117 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v2_4_free_microcode()
148 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_init_microcode()
175 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v2_4_init_microcode()
344 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_gfx_stop()
384 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_enable()
409 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_gfx_resume()
472 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_gfx_resume()
820 adev->sdma.num_instances = SDMA_MAX_INSTANCE; in sdma_v2_4_early_init()
860 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_sw_init()
881 for (i = 0; i < adev->sdma.num_instances; in sdma_v2_4_sw_fini()
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H A Dsdma_v5_2.c369 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_gfx_stop()
428 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_ctx_switch_enable()
467 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_enable()
495 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_gfx_resume()
667 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_load_microcode()
700 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_soft_reset()
1226 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_sw_init()
1240 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_sw_init()
1269 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v5_2_sw_fini()
1319 for (i = 0; i < adev->sdma.num_instances; in sdma_v5_2_is_idle()
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H A Dsdma_v5_0.c243 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_init_microcode()
564 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_gfx_stop()
623 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_ctx_switch_enable()
665 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_enable()
692 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_gfx_resume()
867 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_load_microcode()
1376 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_sw_init()
1406 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v5_0_sw_fini()
1461 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_is_idle()
1636 for (i = 0; i < adev->sdma.num_instances; in sdma_v5_0_update_medium_grain_clock_gating()
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H A Dsdma_v6_0.c386 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_gfx_stop()
422 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_ctxempty_int_enable()
452 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_enable()
478 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_gfx_resume()
548 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); in sdma_v6_0_gfx_resume()
678 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_load_microcode()
728 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_soft_reset()
763 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_check_soft_reset()
1292 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_sw_init()
1327 for (i = 0; i < adev->sdma.num_instances; in sdma_v6_0_sw_fini()
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H A Dsdma_v4_4.c243 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_reset_ras_error_count()
256 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_query_ras_error_count()
H A Damdgpu_sdma.h107 int num_instances; member
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_0.c530 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_setup_ulv()
562 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_destroy_inst_ctx()
642 for (i = 1; i < adev->sdma.num_instances; i++) { in sdma_v4_0_init_microcode()
667 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_init_microcode()
963 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_gfx_stop()
1006 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_page_stop()
1063 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_ctx_switch_enable()
1106 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_enable()
1408 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_load_microcode()
1464 for (i = 0; i < adev->sdma.num_instances; in sdma_v4_0_start()
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H A Dcik_sdma.c76 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_free_microcode()
135 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_init_microcode()
148 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_init_microcode()
317 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_gfx_stop()
374 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_ctx_switch_enable()
412 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_enable()
438 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_gfx_resume()
504 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_gfx_resume()
549 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_load_microcode()
934 adev->sdma.num_instances in cik_sdma_early_init()
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H A Damdgpu_sdma.c41 for (i = 0; i < adev->sdma.num_instances; i++) in amdgpu_sdma_get_instance_from_ring()
54 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_get_index_from_ring()
118 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_ras_late_init()
H A Dsi_dma.c118 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_stop()
137 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_start()
470 adev->sdma.num_instances = 2; in si_dma_early_init()
498 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_sw_init()
521 for (i = 0; i < adev->sdma.num_instances; i++) in si_dma_sw_fini()
655 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_set_clockgating_state()
667 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_set_clockgating_state()
749 for (i = 0; i < adev->sdma.num_instances; i++) in si_dma_set_ring_funcs()
842 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_set_vm_pte_funcs()
846 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in si_dma_set_vm_pte_funcs()
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H A Dsdma_v5_2.c119 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_destroy_inst_ctx()
177 for (i = 1; i < adev->sdma.num_instances; i++) { in sdma_v5_2_init_microcode()
199 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_init_microcode()
471 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_gfx_stop()
530 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_ctx_switch_enable()
565 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_enable()
593 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_gfx_resume()
767 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_load_microcode()
1164 adev->sdma.num_instances = 4; in sdma_v5_2_early_init()
1167 adev->sdma.num_instances in sdma_v5_2_early_init()
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H A Dsdma_v2_4.c116 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_free_microcode()
149 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_init_microcode()
179 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_init_microcode()
350 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_gfx_stop()
390 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_enable()
416 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_gfx_resume()
482 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_gfx_resume()
827 adev->sdma.num_instances = SDMA_MAX_INSTANCE; in sdma_v2_4_early_init()
867 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_sw_init()
890 for (i = 0; i < adev->sdma.num_instances; in sdma_v2_4_sw_fini()
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H A Dsdma_v3_0.c253 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_free_microcode()
307 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_init_microcode()
335 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_init_microcode()
524 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_gfx_stop()
583 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_ctx_switch_enable()
625 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_enable()
653 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_gfx_resume()
754 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_gfx_resume()
1100 adev->sdma.num_instances = 1; in sdma_v3_0_early_init()
1103 adev->sdma.num_instances in sdma_v3_0_early_init()
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H A Dsdma_v5_0.c229 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_init_microcode()
260 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_init_microcode()
533 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_gfx_stop()
592 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_ctx_switch_enable()
634 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_enable()
662 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_gfx_resume()
834 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_load_microcode()
1225 adev->sdma.num_instances = 2; in sdma_v5_0_early_init()
1262 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_sw_init()
1293 for (i = 0; i < adev->sdma.num_instances; in sdma_v5_0_sw_fini()
[all...]
H A Damdgpu_sdma.h67 int num_instances; member
/kernel/linux/linux-5.10/drivers/media/platform/exynos4-is/
H A Dfimc-lite.h60 * @num_instances: total number of FIMC-LITE IP instances available
69 unsigned short num_instances; member
/kernel/linux/linux-5.10/include/sound/
H A Dtimer.h79 int num_instances; /* current number of timer instances */ member

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