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Searched refs:mux_reg (Results 1 - 25 of 55) sorted by relevance

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/kernel/linux/linux-6.6/arch/arm/mach-omap1/
H A Dmux.h28 .mux_reg = FUNC_MUX_CTRL_##reg, \
42 .mux_reg = OMAP7XX_IO_CONF_##reg, \
53 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
65 .mux_reg = OMAP7XX_IO_CONF_##reg, \
75 #define MUX_CFG(desc, mux_reg, mode_offset, mode, \
81 MUX_REG(mux_reg, mode_offset, mode) \
94 #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
99 MUX_REG_7XX(mux_reg, mode_offset, mode) \
100 PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
106 const unsigned int mux_reg; member
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H A Dmux.c295 if (cfg->mux_reg) { in omap1_cfg_reg()
299 reg_orig = omap_readl(cfg->mux_reg); in omap1_cfg_reg()
312 omap_writel(reg, cfg->mux_reg); in omap1_cfg_reg()
371 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); in omap1_cfg_reg()
/kernel/linux/linux-5.10/arch/arm/mach-omap1/include/mach/
H A Dmux.h28 .mux_reg = FUNC_MUX_CTRL_##reg, \
42 .mux_reg = OMAP7XX_IO_CONF_##reg, \
53 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
65 .mux_reg = OMAP7XX_IO_CONF_##reg, \
75 #define MUX_CFG(desc, mux_reg, mode_offset, mode, \
81 MUX_REG(mux_reg, mode_offset, mode) \
94 #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
99 MUX_REG_7XX(mux_reg, mode_offset, mode) \
100 PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
106 const unsigned int mux_reg; member
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/kernel/linux/linux-5.10/drivers/clk/samsung/
H A Dclk-cpu.c88 static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos, in wait_until_mux_stable() argument
94 if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) in wait_until_mux_stable()
98 if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) in wait_until_mux_stable()
155 unsigned long div0, div1 = 0, mux_reg; in exynos_cpuclk_pre_rate_change() local
207 mux_reg = readl(base + E4210_SRC_CPU); in exynos_cpuclk_pre_rate_change()
208 writel(mux_reg | (1 << 16), base + E4210_SRC_CPU); in exynos_cpuclk_pre_rate_change()
231 unsigned long mux_reg; in exynos_cpuclk_post_rate_change() local
246 mux_reg = readl(base + E4210_SRC_CPU); in exynos_cpuclk_post_rate_change()
247 writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU); in exynos_cpuclk_post_rate_change()
283 unsigned long div0, div1 = 0, mux_reg; in exynos5433_cpuclk_pre_rate_change() local
341 unsigned long mux_reg; exynos5433_cpuclk_post_rate_change() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/samsung/
H A Dclk-cpu.c88 static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos, in wait_until_mux_stable() argument
94 if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) in wait_until_mux_stable()
98 if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) in wait_until_mux_stable()
155 unsigned long div0, div1 = 0, mux_reg; in exynos_cpuclk_pre_rate_change() local
207 mux_reg = readl(base + E4210_SRC_CPU); in exynos_cpuclk_pre_rate_change()
208 writel(mux_reg | (1 << 16), base + E4210_SRC_CPU); in exynos_cpuclk_pre_rate_change()
231 unsigned long mux_reg; in exynos_cpuclk_post_rate_change() local
246 mux_reg = readl(base + E4210_SRC_CPU); in exynos_cpuclk_post_rate_change()
247 writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU); in exynos_cpuclk_post_rate_change()
283 unsigned long div0, div1 = 0, mux_reg; in exynos5433_cpuclk_pre_rate_change() local
341 unsigned long mux_reg; exynos5433_cpuclk_post_rate_change() local
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/kernel/linux/linux-6.6/drivers/clk/qcom/
H A Dlpass-gfm-sm8250.c29 unsigned int mux_reg; member
70 .mux_reg = 0x20000,
90 .mux_reg = 0x20000,
110 .mux_reg = 0x220d8,
130 .mux_reg = 0x220d8,
150 .mux_reg = 0x240d8,
170 .mux_reg = 0x240d8,
275 gfm->gfm_mux = gfm->gfm_mux + data->gfm_clks[i]->mux_reg; in lpass_gfm_clk_driver_probe()
/kernel/linux/linux-5.10/drivers/pinctrl/tegra/
H A Dpinctrl-tegra.c260 if (WARN_ON(g->mux_reg < 0)) in tegra_pinctrl_set_mux()
270 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
273 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
291 if (group->mux_reg < 0 || group->sfsel_bit < 0) in tegra_pinctrl_gpio_request_enable()
294 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_request_enable()
296 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_request_enable()
314 if (group->mux_reg < 0 || group->sfsel_bit < 0) in tegra_pinctrl_gpio_disable_free()
317 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_disable_free()
319 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_disable_free()
352 *reg = g->mux_reg; in tegra_pinconf_reg()
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/kernel/linux/linux-6.6/drivers/pinctrl/tegra/
H A Dpinctrl-tegra.c262 if (WARN_ON(g->mux_reg < 0)) in tegra_pinctrl_set_mux()
272 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
275 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
318 if (group->mux_reg < 0 || group->sfsel_bit < 0) in tegra_pinctrl_gpio_request_enable()
321 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_request_enable()
323 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_request_enable()
344 if (group->mux_reg < 0 || group->sfsel_bit < 0) in tegra_pinctrl_gpio_disable_free()
347 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_disable_free()
349 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_disable_free()
382 *reg = g->mux_reg; in tegra_pinconf_reg()
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/kernel/linux/linux-5.10/arch/arm/mach-davinci/
H A Dmux.h23 .mux_reg = PINMUX(muxreg), \
34 .mux_reg = INTMUX, \
45 .mux_reg = EVTMUX, \
H A Dmux.c70 reg_orig = __raw_readl(pinmux_base + cfg->mux_reg); in davinci_cfg_reg()
82 __raw_writel(reg, pinmux_base + cfg->mux_reg); in davinci_cfg_reg()
96 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); in davinci_cfg_reg()
/kernel/linux/linux-5.10/drivers/pinctrl/freescale/
H A Dpinctrl-imx.c174 if (pin_reg->mux_reg == -1) { in imx_pmx_set_one_pin_mmio()
183 reg = readl(ipctl->base + pin_reg->mux_reg); in imx_pmx_set_one_pin_mmio()
186 writel(reg, ipctl->base + pin_reg->mux_reg); in imx_pmx_set_one_pin_mmio()
188 pin_reg->mux_reg, reg); in imx_pmx_set_one_pin_mmio()
190 writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg); in imx_pmx_set_one_pin_mmio()
192 pin_reg->mux_reg, pin_mmio->mux_mode); in imx_pmx_set_one_pin_mmio()
505 * <mux_reg conf_reg input_reg mux_mode input_val>
524 u32 mux_reg, conf_reg; in imx_pinctrl_parse_pin_mmio() local
527 mux_reg = be32_to_cpu(*list++); in imx_pinctrl_parse_pin_mmio()
529 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) in imx_pinctrl_parse_pin_mmio()
[all...]
H A Dpinctrl-imx7ulp.c271 if (pin_reg->mux_reg == -1) in imx7ulp_pmx_gpio_set_direction()
274 reg = readl(ipctl->base + pin_reg->mux_reg); in imx7ulp_pmx_gpio_set_direction()
279 writel(reg, ipctl->base + pin_reg->mux_reg); in imx7ulp_pmx_gpio_set_direction()
H A Dpinctrl-vf610.c302 if (pin_reg->mux_reg == -1) in vf610_pmx_gpio_set_direction()
306 reg = readl(ipctl->base + pin_reg->mux_reg); in vf610_pmx_gpio_set_direction()
311 writel(reg, ipctl->base + pin_reg->mux_reg); in vf610_pmx_gpio_set_direction()
/kernel/linux/linux-6.6/drivers/pinctrl/freescale/
H A Dpinctrl-imx.c176 if (pin_reg->mux_reg == -1) { in imx_pmx_set_one_pin_mmio()
185 reg = readl(ipctl->base + pin_reg->mux_reg); in imx_pmx_set_one_pin_mmio()
188 writel(reg, ipctl->base + pin_reg->mux_reg); in imx_pmx_set_one_pin_mmio()
190 pin_reg->mux_reg, reg); in imx_pmx_set_one_pin_mmio()
192 writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg); in imx_pmx_set_one_pin_mmio()
194 pin_reg->mux_reg, pin_mmio->mux_mode); in imx_pmx_set_one_pin_mmio()
450 * <mux_reg conf_reg input_reg mux_mode input_val>
469 u32 mux_reg, conf_reg; in imx_pinctrl_parse_pin_mmio() local
472 mux_reg = be32_to_cpu(*list++); in imx_pinctrl_parse_pin_mmio()
474 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) in imx_pinctrl_parse_pin_mmio()
[all...]
H A Dpinctrl-imx8ulp.c229 if (pin_reg->mux_reg == -1) in imx8ulp_pmx_gpio_set_direction()
232 reg = readl(ipctl->base + pin_reg->mux_reg); in imx8ulp_pmx_gpio_set_direction()
237 writel(reg, ipctl->base + pin_reg->mux_reg); in imx8ulp_pmx_gpio_set_direction()
H A Dpinctrl-vf610.c302 if (pin_reg->mux_reg == -1) in vf610_pmx_gpio_set_direction()
306 reg = readl(ipctl->base + pin_reg->mux_reg); in vf610_pmx_gpio_set_direction()
311 writel(reg, ipctl->base + pin_reg->mux_reg); in vf610_pmx_gpio_set_direction()
H A Dpinctrl-imx7ulp.c270 if (pin_reg->mux_reg == -1) in imx7ulp_pmx_gpio_set_direction()
273 reg = readl(ipctl->base + pin_reg->mux_reg); in imx7ulp_pmx_gpio_set_direction()
278 writel(reg, ipctl->base + pin_reg->mux_reg); in imx7ulp_pmx_gpio_set_direction()
/kernel/linux/linux-6.6/arch/arm/mach-davinci/
H A Dmux.c68 reg_orig = __raw_readl(pinmux_base + cfg->mux_reg); in davinci_cfg_reg()
80 __raw_writel(reg, pinmux_base + cfg->mux_reg); in davinci_cfg_reg()
94 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); in davinci_cfg_reg()
H A Dmux.h17 const unsigned char mux_reg; member
673 .mux_reg = PINMUX(muxreg), \
684 .mux_reg = INTMUX, \
695 .mux_reg = EVTMUX, \
/kernel/linux/linux-5.10/drivers/clk/mediatek/
H A Dclk-mtk.h65 uint32_t mux_reg; member
85 .mux_reg = _reg, \
121 .mux_reg = _reg, \
/kernel/linux/linux-6.6/drivers/clk/mediatek/
H A Dclk-mtk.h96 uint32_t mux_reg; member
116 .mux_reg = _reg, \
152 .mux_reg = _reg, \
/kernel/linux/linux-5.10/drivers/clk/microchip/
H A Dclk-core.c763 void __iomem *mux_reg; member
824 v = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; in sclk_get_parent()
848 v = readl(sclk->mux_reg); in sclk_set_parent()
854 writel(v, sclk->mux_reg); in sclk_set_parent()
857 writel(OSC_SWEN, PIC32_SET(sclk->mux_reg)); in sclk_set_parent()
875 cosc = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; in sclk_set_parent()
939 sclk->mux_reg = data->mux_reg + core->iobase; in pic32_sys_clk_register()
H A Dclk-core.h29 const u32 mux_reg; member
/kernel/linux/linux-6.6/drivers/clk/microchip/
H A Dclk-core.c763 void __iomem *mux_reg; member
824 v = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; in sclk_get_parent()
848 v = readl(sclk->mux_reg); in sclk_set_parent()
854 writel(v, sclk->mux_reg); in sclk_set_parent()
857 writel(OSC_SWEN, PIC32_SET(sclk->mux_reg)); in sclk_set_parent()
875 cosc = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; in sclk_set_parent()
939 sclk->mux_reg = data->mux_reg + core->iobase; in pic32_sys_clk_register()
/kernel/linux/linux-5.10/arch/arm/mach-omap1/
H A Dmux.c341 if (cfg->mux_reg) { in omap1_cfg_reg()
345 reg_orig = omap_readl(cfg->mux_reg); in omap1_cfg_reg()
358 omap_writel(reg, cfg->mux_reg); in omap1_cfg_reg()
417 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); in omap1_cfg_reg()

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