18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Purna Chandra Mandal,<purna.mandal@microchip.com> 48c2ecf20Sopenharmony_ci * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. 58c2ecf20Sopenharmony_ci */ 68c2ecf20Sopenharmony_ci#ifndef __MICROCHIP_CLK_PIC32_H_ 78c2ecf20Sopenharmony_ci#define __MICROCHIP_CLK_PIC32_H_ 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#include <linux/clk-provider.h> 108c2ecf20Sopenharmony_ci 118c2ecf20Sopenharmony_ci/* PIC32 clock data */ 128c2ecf20Sopenharmony_cistruct pic32_clk_common { 138c2ecf20Sopenharmony_ci struct device *dev; 148c2ecf20Sopenharmony_ci void __iomem *iobase; 158c2ecf20Sopenharmony_ci spinlock_t reg_lock; /* clock lock */ 168c2ecf20Sopenharmony_ci}; 178c2ecf20Sopenharmony_ci 188c2ecf20Sopenharmony_ci/* System PLL clock */ 198c2ecf20Sopenharmony_cistruct pic32_sys_pll_data { 208c2ecf20Sopenharmony_ci struct clk_init_data init_data; 218c2ecf20Sopenharmony_ci const u32 ctrl_reg; 228c2ecf20Sopenharmony_ci const u32 status_reg; 238c2ecf20Sopenharmony_ci const u32 lock_mask; 248c2ecf20Sopenharmony_ci}; 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci/* System clock */ 278c2ecf20Sopenharmony_cistruct pic32_sys_clk_data { 288c2ecf20Sopenharmony_ci struct clk_init_data init_data; 298c2ecf20Sopenharmony_ci const u32 mux_reg; 308c2ecf20Sopenharmony_ci const u32 slew_reg; 318c2ecf20Sopenharmony_ci const u32 *parent_map; 328c2ecf20Sopenharmony_ci const u32 slew_div; 338c2ecf20Sopenharmony_ci}; 348c2ecf20Sopenharmony_ci 358c2ecf20Sopenharmony_ci/* Reference Oscillator clock */ 368c2ecf20Sopenharmony_cistruct pic32_ref_osc_data { 378c2ecf20Sopenharmony_ci struct clk_init_data init_data; 388c2ecf20Sopenharmony_ci const u32 ctrl_reg; 398c2ecf20Sopenharmony_ci const u32 *parent_map; 408c2ecf20Sopenharmony_ci}; 418c2ecf20Sopenharmony_ci 428c2ecf20Sopenharmony_ci/* Peripheral Bus clock */ 438c2ecf20Sopenharmony_cistruct pic32_periph_clk_data { 448c2ecf20Sopenharmony_ci struct clk_init_data init_data; 458c2ecf20Sopenharmony_ci const u32 ctrl_reg; 468c2ecf20Sopenharmony_ci}; 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ci/* External Secondary Oscillator clock */ 498c2ecf20Sopenharmony_cistruct pic32_sec_osc_data { 508c2ecf20Sopenharmony_ci struct clk_init_data init_data; 518c2ecf20Sopenharmony_ci const u32 enable_reg; 528c2ecf20Sopenharmony_ci const u32 status_reg; 538c2ecf20Sopenharmony_ci const u32 enable_mask; 548c2ecf20Sopenharmony_ci const u32 status_mask; 558c2ecf20Sopenharmony_ci const unsigned long fixed_rate; 568c2ecf20Sopenharmony_ci}; 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_ciextern const struct clk_ops pic32_pbclk_ops; 598c2ecf20Sopenharmony_ciextern const struct clk_ops pic32_sclk_ops; 608c2ecf20Sopenharmony_ciextern const struct clk_ops pic32_sclk_no_div_ops; 618c2ecf20Sopenharmony_ciextern const struct clk_ops pic32_spll_ops; 628c2ecf20Sopenharmony_ciextern const struct clk_ops pic32_roclk_ops; 638c2ecf20Sopenharmony_ciextern const struct clk_ops pic32_sosc_ops; 648c2ecf20Sopenharmony_ci 658c2ecf20Sopenharmony_cistruct clk *pic32_periph_clk_register(const struct pic32_periph_clk_data *data, 668c2ecf20Sopenharmony_ci struct pic32_clk_common *core); 678c2ecf20Sopenharmony_cistruct clk *pic32_refo_clk_register(const struct pic32_ref_osc_data *data, 688c2ecf20Sopenharmony_ci struct pic32_clk_common *core); 698c2ecf20Sopenharmony_cistruct clk *pic32_sys_clk_register(const struct pic32_sys_clk_data *data, 708c2ecf20Sopenharmony_ci struct pic32_clk_common *core); 718c2ecf20Sopenharmony_cistruct clk *pic32_spll_clk_register(const struct pic32_sys_pll_data *data, 728c2ecf20Sopenharmony_ci struct pic32_clk_common *core); 738c2ecf20Sopenharmony_cistruct clk *pic32_sosc_clk_register(const struct pic32_sec_osc_data *data, 748c2ecf20Sopenharmony_ci struct pic32_clk_common *core); 758c2ecf20Sopenharmony_ci 768c2ecf20Sopenharmony_ci#endif /* __MICROCHIP_CLK_PIC32_H_*/ 77