/kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
H A D | omap_hwmod_2xxx_ipblock_data.c | 189 .main_clk = "mpu_ck", 201 .main_clk = "gpt3_fck", 216 .main_clk = "gpt4_fck", 231 .main_clk = "gpt5_fck", 246 .main_clk = "gpt6_fck", 261 .main_clk = "gpt7_fck", 276 .main_clk = "gpt8_fck", 291 .main_clk = "gpt9_fck", 306 .main_clk = "gpt10_fck", 321 .main_clk [all...] |
H A D | omap_hwmod_2430_data.c | 51 .main_clk = "dsp_fck", 74 .main_clk = "i2chs1_fck", 97 .main_clk = "i2chs2_fck", 112 .main_clk = "gpio5_fck", 127 .main_clk = "mailboxes_ick", 140 .main_clk = "mcspi3_fck", 172 .main_clk = "usbhs_ick", 216 .main_clk = "mcbsp1_fck", 232 .main_clk = "mcbsp2_fck", 248 .main_clk [all...] |
H A D | omap_hwmod_81xx_data.c | 175 .main_clk = "mpu_ck", 202 .main_clk = "mpu_ck", 244 .main_clk = "sysclk18_ck", 281 .main_clk = "sysclk10_ck", 302 .main_clk = "sysclk10_ck", 323 .main_clk = "sysclk10_ck", 360 .main_clk = "sysclk18_ck", 398 .main_clk = "sysclk10_ck", 418 .main_clk = "sysclk10_ck", 455 .main_clk [all...] |
H A D | omap_hwmod_33xx_data.c | 36 .main_clk = "dpll_ddr_m2_div2_ck", 51 .main_clk = "l4hs_gclk", 71 .main_clk = "dpll_core_m4_div2_ck", 109 .main_clk = "cefuse_fck", 129 .main_clk = "clkdiv32k_ick", 147 .main_clk = "l4ls_gclk", 174 .main_clk = "trace_clk_div_ck", 190 .main_clk = "dpll_core_m4_div2_ck",
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H A D | omap_hwmod_3xxx_data.c | 88 .main_clk = "arm_fck", 104 .main_clk = "iva2_ck", 128 .main_clk = "emu_src_ck", 153 .main_clk = "gpt3_fck", 168 .main_clk = "gpt4_fck", 183 .main_clk = "gpt5_fck", 198 .main_clk = "gpt6_fck", 213 .main_clk = "gpt7_fck", 228 .main_clk = "gpt8_fck", 243 .main_clk [all...] |
H A D | omap_hwmod_33xx_43xx_ipblock_data.c | 43 .main_clk = "l3_gclk", 64 .main_clk = "l3_gclk", 86 .main_clk = "l4ls_gclk", 119 .main_clk = "dpll_mpu_m2_ck", 175 .main_clk = "l3_gclk", 193 .main_clk = "smartreflex0_fck", 206 .main_clk = "smartreflex1_fck", 244 .main_clk = "l3s_gclk",
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H A D | omap_hwmod_2420_data.c | 56 .main_clk = "iva1_ifck", 75 .main_clk = "dsp_fck", 96 .main_clk = "i2c1_fck", 116 .main_clk = "i2c2_fck", 132 .main_clk = "mailboxes_ick", 160 .main_clk = "mcbsp1_fck", 176 .main_clk = "mcbsp2_fck", 206 .main_clk = "mmc_fck", 220 .main_clk = "hdq_fck",
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H A D | omap_hwmod_7xx_data.c | 190 .main_clk = "atl_gfclk_mux", 214 .main_clk = "dpll_core_h24x2_ck", 273 .main_clk = "l3_iclk_div", 300 .main_clk = "dpll_mpu_m2_ck", 353 .main_clk = "l4_root_clk_div", 376 .main_clk = "l4_root_clk_div", 411 .main_clk = "qspi_gfclk_div", 448 .main_clk = "func_48m_fclk", 473 .main_clk = "l3_iclk_div", 487 .main_clk [all...] |
H A D | omap_hwmod_43xx_data.c | 28 .main_clk = "dpll_ddr_m2_ck", 42 .main_clk = "l4hs_gclk", 61 .main_clk = "sys_clkin_ck", 79 .main_clk = "sys_clkin_ck",
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H A D | omap_hwmod_54xx_data.c | 203 .main_clk = "dpll_core_h11x2_ck", 219 .main_clk = "dpll_core_h11x2_ck", 247 .main_clk = "dpll_mpu_m2_ck", 282 .main_clk = "func_48m_fclk",
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H A D | omap_hwmod_44xx_data.c | 301 .main_clk = "trace_clk_div_ck", 330 .main_clk = "ddrphy_ck", 346 .main_clk = "ddrphy_ck", 431 .main_clk = "ducati_clk_mux_ck", 465 .main_clk = "dpll_iva_m5x2_ck", 491 .main_clk = "dpll_mpu_m2_ck",
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H A D | omap_hwmod.h | 437 * operate and they need to be handled at the same time as the main_clk. 538 * @main_clk: main clock: OMAP clock name 559 * @main_clk refers to this module's "main clock," which for our 584 const char *main_clk; member
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H A D | omap_hwmod.c | 819 * or a main_clk is present. Returns 0 on success or -EINVAL on error. 829 pr_debug("%s: mapped main_clk %s for %s\n", __func__, in _init_main_clk() 831 oh->main_clk = __clk_get_name(clk); in _init_main_clk() 835 if (!oh->main_clk) in _init_main_clk() 838 oh->_clk = clk_get(NULL, oh->main_clk); in _init_main_clk() 842 pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n", in _init_main_clk() 843 oh->name, oh->main_clk); in _init_main_clk() 858 oh->name, oh->main_clk); in _init_main_clk() 2884 * will be using its main_clk to enable/disable the module. Returns 4071 return oh->main_clk; in omap_hwmod_get_main_clk() [all...] |
H A D | omap_device.c | 113 _add_clkdev(od, "fck", oh->main_clk); in _add_hwmod_clocks_clkdev()
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/kernel/linux/linux-6.6/arch/arm/mach-omap2/ |
H A D | omap_hwmod_2xxx_ipblock_data.c | 189 .main_clk = "mpu_ck", 195 .main_clk = "gpt3_fck", 210 .main_clk = "gpt4_fck", 225 .main_clk = "gpt5_fck", 240 .main_clk = "gpt6_fck", 255 .main_clk = "gpt7_fck", 270 .main_clk = "gpt8_fck", 285 .main_clk = "gpt9_fck", 300 .main_clk = "gpt10_fck", 315 .main_clk [all...] |
H A D | omap_hwmod_2430_data.c | 51 .main_clk = "dsp_fck", 74 .main_clk = "i2chs1_fck", 97 .main_clk = "i2chs2_fck", 112 .main_clk = "gpio5_fck", 127 .main_clk = "mailboxes_ick", 140 .main_clk = "mcspi3_fck", 172 .main_clk = "usbhs_ick", 216 .main_clk = "mcbsp1_fck", 232 .main_clk = "mcbsp2_fck", 248 .main_clk [all...] |
H A D | omap_hwmod_81xx_data.c | 166 .main_clk = "mpu_ck", 193 .main_clk = "mpu_ck", 235 .main_clk = "sysclk18_ck", 272 .main_clk = "sysclk10_ck", 293 .main_clk = "sysclk10_ck", 314 .main_clk = "sysclk10_ck", 351 .main_clk = "sysclk18_ck", 389 .main_clk = "sysclk10_ck", 409 .main_clk = "sysclk10_ck", 446 .main_clk [all...] |
H A D | omap_hwmod_3xxx_data.c | 87 .main_clk = "arm_fck", 103 .main_clk = "iva2_ck", 127 .main_clk = "emu_src_ck", 152 .main_clk = "gpt3_fck", 167 .main_clk = "gpt4_fck", 182 .main_clk = "gpt5_fck", 197 .main_clk = "gpt6_fck", 212 .main_clk = "gpt7_fck", 227 .main_clk = "gpt8_fck", 242 .main_clk [all...] |
H A D | omap_hwmod_2420_data.c | 55 .main_clk = "iva1_ifck", 74 .main_clk = "dsp_fck", 95 .main_clk = "i2c1_fck", 115 .main_clk = "i2c2_fck", 131 .main_clk = "mailboxes_ick", 159 .main_clk = "mcbsp1_fck", 175 .main_clk = "mcbsp2_fck", 205 .main_clk = "mmc_fck", 219 .main_clk = "hdq_fck",
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H A D | omap_hwmod.h | 437 * operate and they need to be handled at the same time as the main_clk. 538 * @main_clk: main clock: OMAP clock name 559 * @main_clk refers to this module's "main clock," which for our 584 const char *main_clk; member
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H A D | omap_hwmod.c | 819 * or a main_clk is present. Returns 0 on success or -EINVAL on error. 829 pr_debug("%s: mapped main_clk %s for %s\n", __func__, in _init_main_clk() 831 oh->main_clk = __clk_get_name(clk); in _init_main_clk() 835 if (!oh->main_clk) in _init_main_clk() 838 oh->_clk = clk_get(NULL, oh->main_clk); in _init_main_clk() 842 pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n", in _init_main_clk() 843 oh->name, oh->main_clk); in _init_main_clk() 858 oh->name, oh->main_clk); in _init_main_clk() 2852 * will be using its main_clk to enable/disable the module. Returns
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H A D | omap_device.c | 116 _add_clkdev(od, "fck", oh->main_clk); in _add_hwmod_clocks_clkdev()
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/kernel/linux/linux-6.6/drivers/input/touchscreen/ |
H A D | goodix_fwupload.c | 311 u32 main_clk = 54; /* Default main clock */ in goodix_send_main_clock() local 316 "goodix,main-clk", &main_clk); in goodix_send_main_clock() 319 ts->main_clk[i] = main_clk; in goodix_send_main_clock() 320 checksum += main_clk; in goodix_send_main_clock() 324 ts->main_clk[GOODIX_MAIN_CLK_LEN - 1] = 256 - checksum; in goodix_send_main_clock() 327 ts->main_clk, GOODIX_MAIN_CLK_LEN); in goodix_send_main_clock()
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H A D | goodix.h | 104 u8 main_clk[GOODIX_MAIN_CLK_LEN]; member
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/kernel/linux/linux-6.6/drivers/soc/mediatek/ |
H A D | mtk-svs.c | 319 * @main_clk: main clock for svs bank 333 struct clk *main_clk; member 1578 clk_disable_unprepare(svsp->main_clk); in svs_suspend() 1588 ret = clk_prepare_enable(svsp->main_clk); in svs_resume() 1590 dev_err(svsp->dev, "cannot enable main_clk, disable svs\n"); in svs_resume() 1613 clk_disable_unprepare(svsp->main_clk); in svs_resume() 2357 svsp->main_clk = devm_clk_get(svsp->dev, "main"); in svs_probe() 2358 if (IS_ERR(svsp->main_clk)) { in svs_probe() 2360 PTR_ERR(svsp->main_clk)); in svs_probe() 2361 ret = PTR_ERR(svsp->main_clk); in svs_probe() [all...] |