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Searched refs:ioaddr (Results 1 - 25 of 608) sorted by relevance

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/kernel/linux/linux-5.10/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_core.c21 static void sxgbe_core_init(void __iomem *ioaddr) in sxgbe_core_init() argument
26 regval = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_core_init()
31 writel(regval, ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_core_init()
34 regval = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_core_init()
40 writel(regval, ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_core_init()
44 static void sxgbe_core_dump_regs(void __iomem *ioaddr) in sxgbe_core_dump_regs() argument
48 static int sxgbe_get_lpi_status(void __iomem *ioaddr, const u32 irq_status) in sxgbe_get_lpi_status() argument
54 lpi_status = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); in sxgbe_get_lpi_status()
69 static int sxgbe_core_host_irq_status(void __iomem *ioaddr, in sxgbe_core_host_irq_status() argument
74 irq_status = readl(ioaddr in sxgbe_core_host_irq_status()
83 sxgbe_core_pmt(void __iomem *ioaddr, unsigned long mode) sxgbe_core_pmt() argument
88 sxgbe_core_set_umac_addr(void __iomem *ioaddr, unsigned char *addr, unsigned int reg_n) sxgbe_core_set_umac_addr() argument
100 sxgbe_core_get_umac_addr(void __iomem *ioaddr, unsigned char *addr, unsigned int reg_n) sxgbe_core_get_umac_addr() argument
117 sxgbe_enable_tx(void __iomem *ioaddr, bool enable) sxgbe_enable_tx() argument
129 sxgbe_enable_rx(void __iomem *ioaddr, bool enable) sxgbe_enable_rx() argument
141 sxgbe_get_controller_version(void __iomem *ioaddr) sxgbe_get_controller_version() argument
147 sxgbe_get_hw_feature(void __iomem *ioaddr, unsigned char feature_index) sxgbe_get_hw_feature() argument
153 sxgbe_core_set_speed(void __iomem *ioaddr, unsigned char speed) sxgbe_core_set_speed() argument
165 sxgbe_core_enable_rxqueue(void __iomem *ioaddr, int queue_num) sxgbe_core_enable_rxqueue() argument
175 sxgbe_core_disable_rxqueue(void __iomem *ioaddr, int queue_num) sxgbe_core_disable_rxqueue() argument
185 sxgbe_set_eee_mode(void __iomem *ioaddr) sxgbe_set_eee_mode() argument
199 sxgbe_reset_eee_mode(void __iomem *ioaddr) sxgbe_reset_eee_mode() argument
208 sxgbe_set_eee_pls(void __iomem *ioaddr, const int link) sxgbe_set_eee_pls() argument
223 sxgbe_set_eee_timer(void __iomem *ioaddr, const int ls, const int tw) sxgbe_set_eee_timer() argument
238 sxgbe_enable_rx_csum(void __iomem *ioaddr) sxgbe_enable_rx_csum() argument
247 sxgbe_disable_rx_csum(void __iomem *ioaddr) sxgbe_disable_rx_csum() argument
[all...]
H A Dsxgbe_mtl.c20 static void sxgbe_mtl_init(void __iomem *ioaddr, unsigned int etsalg, in sxgbe_mtl_init() argument
25 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
40 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
50 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
54 static void sxgbe_mtl_dma_dm_rxqueue(void __iomem *ioaddr) in sxgbe_mtl_dma_dm_rxqueue() argument
56 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP0_REG); in sxgbe_mtl_dma_dm_rxqueue()
57 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP1_REG); in sxgbe_mtl_dma_dm_rxqueue()
58 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP2_REG); in sxgbe_mtl_dma_dm_rxqueue()
61 static void sxgbe_mtl_set_txfifosize(void __iomem *ioaddr, int queue_num, in sxgbe_mtl_set_txfifosize() argument
68 reg_val = readl(ioaddr in sxgbe_mtl_set_txfifosize()
73 sxgbe_mtl_set_rxfifosize(void __iomem *ioaddr, int queue_num, int queue_fifo) sxgbe_mtl_set_rxfifosize() argument
85 sxgbe_mtl_enable_txqueue(void __iomem *ioaddr, int queue_num) sxgbe_mtl_enable_txqueue() argument
94 sxgbe_mtl_disable_txqueue(void __iomem *ioaddr, int queue_num) sxgbe_mtl_disable_txqueue() argument
103 sxgbe_mtl_fc_active(void __iomem *ioaddr, int queue_num, int threshold) sxgbe_mtl_fc_active() argument
115 sxgbe_mtl_fc_enable(void __iomem *ioaddr, int queue_num) sxgbe_mtl_fc_enable() argument
124 sxgbe_mtl_fc_deactive(void __iomem *ioaddr, int queue_num, int threshold) sxgbe_mtl_fc_deactive() argument
136 sxgbe_mtl_fep_enable(void __iomem *ioaddr, int queue_num) sxgbe_mtl_fep_enable() argument
146 sxgbe_mtl_fep_disable(void __iomem *ioaddr, int queue_num) sxgbe_mtl_fep_disable() argument
156 sxgbe_mtl_fup_enable(void __iomem *ioaddr, int queue_num) sxgbe_mtl_fup_enable() argument
166 sxgbe_mtl_fup_disable(void __iomem *ioaddr, int queue_num) sxgbe_mtl_fup_disable() argument
177 sxgbe_set_tx_mtl_mode(void __iomem *ioaddr, int queue_num, int tx_mode) sxgbe_set_tx_mtl_mode() argument
208 sxgbe_set_rx_mtl_mode(void __iomem *ioaddr, int queue_num, int rx_mode) sxgbe_set_rx_mtl_mode() argument
[all...]
H A Dsxgbe_dma.c21 static int sxgbe_dma_init(void __iomem *ioaddr, int fix_burst, int burst_map) in sxgbe_dma_init() argument
25 reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
38 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
43 static void sxgbe_dma_channel_init(void __iomem *ioaddr, int cha_num, in sxgbe_dma_channel_init() argument
50 reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
54 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
56 reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
58 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
60 reg_val = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
62 writel(reg_val, ioaddr in sxgbe_dma_channel_init()
96 sxgbe_enable_dma_transmission(void __iomem *ioaddr, int cha_num) sxgbe_enable_dma_transmission() argument
105 sxgbe_enable_dma_irq(void __iomem *ioaddr, int dma_cnum) sxgbe_enable_dma_irq() argument
112 sxgbe_disable_dma_irq(void __iomem *ioaddr, int dma_cnum) sxgbe_disable_dma_irq() argument
118 sxgbe_dma_start_tx(void __iomem *ioaddr, int tchannels) sxgbe_dma_start_tx() argument
131 sxgbe_dma_start_tx_queue(void __iomem *ioaddr, int dma_cnum) sxgbe_dma_start_tx_queue() argument
140 sxgbe_dma_stop_tx_queue(void __iomem *ioaddr, int dma_cnum) sxgbe_dma_stop_tx_queue() argument
149 sxgbe_dma_stop_tx(void __iomem *ioaddr, int tchannels) sxgbe_dma_stop_tx() argument
161 sxgbe_dma_start_rx(void __iomem *ioaddr, int rchannels) sxgbe_dma_start_rx() argument
174 sxgbe_dma_stop_rx(void __iomem *ioaddr, int rchannels) sxgbe_dma_stop_rx() argument
186 sxgbe_tx_dma_int_status(void __iomem *ioaddr, int channel_no, struct sxgbe_extra_stats *x) sxgbe_tx_dma_int_status() argument
258 sxgbe_rx_dma_int_status(void __iomem *ioaddr, int channel_no, struct sxgbe_extra_stats *x) sxgbe_rx_dma_int_status() argument
325 sxgbe_dma_rx_watchdog(void __iomem *ioaddr, u32 riwt) sxgbe_dma_rx_watchdog() argument
335 sxgbe_enable_tso(void __iomem *ioaddr, u8 chan_num) sxgbe_enable_tso() argument
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_core.c21 static void sxgbe_core_init(void __iomem *ioaddr) in sxgbe_core_init() argument
26 regval = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_core_init()
31 writel(regval, ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_core_init()
34 regval = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_core_init()
40 writel(regval, ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_core_init()
44 static void sxgbe_core_dump_regs(void __iomem *ioaddr) in sxgbe_core_dump_regs() argument
48 static int sxgbe_get_lpi_status(void __iomem *ioaddr, const u32 irq_status) in sxgbe_get_lpi_status() argument
54 lpi_status = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); in sxgbe_get_lpi_status()
69 static int sxgbe_core_host_irq_status(void __iomem *ioaddr, in sxgbe_core_host_irq_status() argument
74 irq_status = readl(ioaddr in sxgbe_core_host_irq_status()
83 sxgbe_core_pmt(void __iomem *ioaddr, unsigned long mode) sxgbe_core_pmt() argument
88 sxgbe_core_set_umac_addr(void __iomem *ioaddr, const unsigned char *addr, unsigned int reg_n) sxgbe_core_set_umac_addr() argument
101 sxgbe_core_get_umac_addr(void __iomem *ioaddr, unsigned char *addr, unsigned int reg_n) sxgbe_core_get_umac_addr() argument
118 sxgbe_enable_tx(void __iomem *ioaddr, bool enable) sxgbe_enable_tx() argument
130 sxgbe_enable_rx(void __iomem *ioaddr, bool enable) sxgbe_enable_rx() argument
142 sxgbe_get_controller_version(void __iomem *ioaddr) sxgbe_get_controller_version() argument
148 sxgbe_get_hw_feature(void __iomem *ioaddr, unsigned char feature_index) sxgbe_get_hw_feature() argument
154 sxgbe_core_set_speed(void __iomem *ioaddr, unsigned char speed) sxgbe_core_set_speed() argument
166 sxgbe_core_enable_rxqueue(void __iomem *ioaddr, int queue_num) sxgbe_core_enable_rxqueue() argument
176 sxgbe_core_disable_rxqueue(void __iomem *ioaddr, int queue_num) sxgbe_core_disable_rxqueue() argument
186 sxgbe_set_eee_mode(void __iomem *ioaddr) sxgbe_set_eee_mode() argument
200 sxgbe_reset_eee_mode(void __iomem *ioaddr) sxgbe_reset_eee_mode() argument
209 sxgbe_set_eee_pls(void __iomem *ioaddr, const int link) sxgbe_set_eee_pls() argument
224 sxgbe_set_eee_timer(void __iomem *ioaddr, const int ls, const int tw) sxgbe_set_eee_timer() argument
239 sxgbe_enable_rx_csum(void __iomem *ioaddr) sxgbe_enable_rx_csum() argument
248 sxgbe_disable_rx_csum(void __iomem *ioaddr) sxgbe_disable_rx_csum() argument
[all...]
H A Dsxgbe_mtl.c20 static void sxgbe_mtl_init(void __iomem *ioaddr, unsigned int etsalg, in sxgbe_mtl_init() argument
25 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
40 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
50 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
54 static void sxgbe_mtl_dma_dm_rxqueue(void __iomem *ioaddr) in sxgbe_mtl_dma_dm_rxqueue() argument
56 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP0_REG); in sxgbe_mtl_dma_dm_rxqueue()
57 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP1_REG); in sxgbe_mtl_dma_dm_rxqueue()
58 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP2_REG); in sxgbe_mtl_dma_dm_rxqueue()
61 static void sxgbe_mtl_set_txfifosize(void __iomem *ioaddr, int queue_num, in sxgbe_mtl_set_txfifosize() argument
68 reg_val = readl(ioaddr in sxgbe_mtl_set_txfifosize()
73 sxgbe_mtl_set_rxfifosize(void __iomem *ioaddr, int queue_num, int queue_fifo) sxgbe_mtl_set_rxfifosize() argument
85 sxgbe_mtl_enable_txqueue(void __iomem *ioaddr, int queue_num) sxgbe_mtl_enable_txqueue() argument
94 sxgbe_mtl_disable_txqueue(void __iomem *ioaddr, int queue_num) sxgbe_mtl_disable_txqueue() argument
103 sxgbe_mtl_fc_active(void __iomem *ioaddr, int queue_num, int threshold) sxgbe_mtl_fc_active() argument
115 sxgbe_mtl_fc_enable(void __iomem *ioaddr, int queue_num) sxgbe_mtl_fc_enable() argument
124 sxgbe_mtl_fc_deactive(void __iomem *ioaddr, int queue_num, int threshold) sxgbe_mtl_fc_deactive() argument
136 sxgbe_mtl_fep_enable(void __iomem *ioaddr, int queue_num) sxgbe_mtl_fep_enable() argument
146 sxgbe_mtl_fep_disable(void __iomem *ioaddr, int queue_num) sxgbe_mtl_fep_disable() argument
156 sxgbe_mtl_fup_enable(void __iomem *ioaddr, int queue_num) sxgbe_mtl_fup_enable() argument
166 sxgbe_mtl_fup_disable(void __iomem *ioaddr, int queue_num) sxgbe_mtl_fup_disable() argument
177 sxgbe_set_tx_mtl_mode(void __iomem *ioaddr, int queue_num, int tx_mode) sxgbe_set_tx_mtl_mode() argument
208 sxgbe_set_rx_mtl_mode(void __iomem *ioaddr, int queue_num, int rx_mode) sxgbe_set_rx_mtl_mode() argument
[all...]
H A Dsxgbe_dma.c21 static int sxgbe_dma_init(void __iomem *ioaddr, int fix_burst, int burst_map) in sxgbe_dma_init() argument
25 reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
38 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
43 static void sxgbe_dma_channel_init(void __iomem *ioaddr, int cha_num, in sxgbe_dma_channel_init() argument
50 reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
54 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
56 reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
58 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
60 reg_val = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
62 writel(reg_val, ioaddr in sxgbe_dma_channel_init()
96 sxgbe_enable_dma_transmission(void __iomem *ioaddr, int cha_num) sxgbe_enable_dma_transmission() argument
105 sxgbe_enable_dma_irq(void __iomem *ioaddr, int dma_cnum) sxgbe_enable_dma_irq() argument
112 sxgbe_disable_dma_irq(void __iomem *ioaddr, int dma_cnum) sxgbe_disable_dma_irq() argument
118 sxgbe_dma_start_tx(void __iomem *ioaddr, int tchannels) sxgbe_dma_start_tx() argument
131 sxgbe_dma_start_tx_queue(void __iomem *ioaddr, int dma_cnum) sxgbe_dma_start_tx_queue() argument
140 sxgbe_dma_stop_tx_queue(void __iomem *ioaddr, int dma_cnum) sxgbe_dma_stop_tx_queue() argument
149 sxgbe_dma_stop_tx(void __iomem *ioaddr, int tchannels) sxgbe_dma_stop_tx() argument
161 sxgbe_dma_start_rx(void __iomem *ioaddr, int rchannels) sxgbe_dma_start_rx() argument
174 sxgbe_dma_stop_rx(void __iomem *ioaddr, int rchannels) sxgbe_dma_stop_rx() argument
186 sxgbe_tx_dma_int_status(void __iomem *ioaddr, int channel_no, struct sxgbe_extra_stats *x) sxgbe_tx_dma_int_status() argument
258 sxgbe_rx_dma_int_status(void __iomem *ioaddr, int channel_no, struct sxgbe_extra_stats *x) sxgbe_rx_dma_int_status() argument
325 sxgbe_dma_rx_watchdog(void __iomem *ioaddr, u32 riwt) sxgbe_dma_rx_watchdog() argument
335 sxgbe_enable_tso(void __iomem *ioaddr, u8 chan_num) sxgbe_enable_tso() argument
[all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac4_lib.c15 int dwmac4_dma_reset(void __iomem *ioaddr) in dwmac4_dma_reset() argument
17 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset()
21 writel(value, ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset()
23 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, in dwmac4_dma_reset()
28 void dwmac4_set_rx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan) in dwmac4_set_rx_tail_ptr() argument
30 writel(tail_ptr, ioaddr + DMA_CHAN_RX_END_ADDR(chan)); in dwmac4_set_rx_tail_ptr()
33 void dwmac4_set_tx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan) in dwmac4_set_tx_tail_ptr() argument
35 writel(tail_ptr, ioaddr + DMA_CHAN_TX_END_ADDR(chan)); in dwmac4_set_tx_tail_ptr()
38 void dwmac4_dma_start_tx(void __iomem *ioaddr, u32 chan) in dwmac4_dma_start_tx() argument
40 u32 value = readl(ioaddr in dwmac4_dma_start_tx()
50 dwmac4_dma_stop_tx(void __iomem *ioaddr, u32 chan) dwmac4_dma_stop_tx() argument
58 dwmac4_dma_start_rx(void __iomem *ioaddr, u32 chan) dwmac4_dma_start_rx() argument
71 dwmac4_dma_stop_rx(void __iomem *ioaddr, u32 chan) dwmac4_dma_stop_rx() argument
79 dwmac4_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan) dwmac4_set_tx_ring_len() argument
84 dwmac4_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan) dwmac4_set_rx_ring_len() argument
89 dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) dwmac4_enable_dma_irq() argument
101 dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) dwmac410_enable_dma_irq() argument
113 dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) dwmac4_disable_dma_irq() argument
125 dwmac410_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) dwmac410_disable_dma_irq() argument
137 dwmac4_dma_interrupt(void __iomem *ioaddr, struct stmmac_extra_stats *x, u32 chan) dwmac4_dma_interrupt() argument
183 stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6], unsigned int high, unsigned int low) stmmac_dwmac4_set_mac_addr() argument
200 stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable) stmmac_dwmac4_set_mac() argument
212 stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, unsigned int high, unsigned int low) stmmac_dwmac4_get_mac_addr() argument
[all...]
H A Ddwxgmac2_dma.c11 static int dwxgmac2_dma_reset(void __iomem *ioaddr) in dwxgmac2_dma_reset() argument
13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value, in dwxgmac2_dma_reset()
22 static void dwxgmac2_dma_init(void __iomem *ioaddr, in dwxgmac2_dma_init() argument
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
33 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
36 static void dwxgmac2_dma_init_chan(void __iomem *ioaddr, in dwxgmac2_dma_init_chan() argument
39 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan()
44 writel(value, ioaddr in dwxgmac2_dma_init_chan()
48 dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, dma_addr_t phy, u32 chan) dwxgmac2_dma_init_rx_chan() argument
64 dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, dma_addr_t phy, u32 chan) dwxgmac2_dma_init_tx_chan() argument
81 dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) dwxgmac2_dma_axi() argument
134 dwxgmac2_dma_dump_regs(void __iomem *ioaddr, u32 *reg_space) dwxgmac2_dma_dump_regs() argument
142 dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode, u32 channel, int fifosz, u8 qmode) dwxgmac2_dma_rx_mode() argument
208 dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode, u32 channel, int fifosz, u8 qmode) dwxgmac2_dma_tx_mode() argument
251 dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) dwxgmac2_enable_dma_irq() argument
264 dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) dwxgmac2_disable_dma_irq() argument
277 dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan) dwxgmac2_dma_start_tx() argument
290 dwxgmac2_dma_stop_tx(void __iomem *ioaddr, u32 chan) dwxgmac2_dma_stop_tx() argument
303 dwxgmac2_dma_start_rx(void __iomem *ioaddr, u32 chan) dwxgmac2_dma_start_rx() argument
316 dwxgmac2_dma_stop_rx(void __iomem *ioaddr, u32 chan) dwxgmac2_dma_stop_rx() argument
325 dwxgmac2_dma_interrupt(void __iomem *ioaddr, struct stmmac_extra_stats *x, u32 chan) dwxgmac2_dma_interrupt() argument
368 dwxgmac2_get_hw_feature(void __iomem *ioaddr, struct dma_features *dma_cap) dwxgmac2_get_hw_feature() argument
446 dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 nchan) dwxgmac2_rx_watchdog() argument
454 dwxgmac2_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan) dwxgmac2_set_rx_ring_len() argument
459 dwxgmac2_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan) dwxgmac2_set_tx_ring_len() argument
464 dwxgmac2_set_rx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan) dwxgmac2_set_rx_tail_ptr() argument
469 dwxgmac2_set_tx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan) dwxgmac2_set_tx_tail_ptr() argument
474 dwxgmac2_enable_tso(void __iomem *ioaddr, bool en, u32 chan) dwxgmac2_enable_tso() argument
486 dwxgmac2_qmode(void __iomem *ioaddr, u32 channel, u8 qmode) dwxgmac2_qmode() argument
503 dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan) dwxgmac2_set_bfsize() argument
513 dwxgmac2_enable_sph(void __iomem *ioaddr, bool en, u32 chan) dwxgmac2_enable_sph() argument
529 dwxgmac2_enable_tbs(void __iomem *ioaddr, bool en, u32 chan) dwxgmac2_enable_tbs() argument
[all...]
H A Ddwmac5.c78 void __iomem *ioaddr, bool correctable, in dwmac5_handle_mac_err()
83 value = readl(ioaddr + MAC_DPP_FSM_INT_STATUS); in dwmac5_handle_mac_err()
84 writel(value, ioaddr + MAC_DPP_FSM_INT_STATUS); in dwmac5_handle_mac_err()
126 void __iomem *ioaddr, bool correctable, in dwmac5_handle_mtl_err()
131 value = readl(ioaddr + MTL_ECC_INT_STATUS); in dwmac5_handle_mtl_err()
132 writel(value, ioaddr + MTL_ECC_INT_STATUS); in dwmac5_handle_mtl_err()
174 void __iomem *ioaddr, bool correctable, in dwmac5_handle_dma_err()
179 value = readl(ioaddr + DMA_ECC_INT_STATUS); in dwmac5_handle_dma_err()
180 writel(value, ioaddr + DMA_ECC_INT_STATUS); in dwmac5_handle_dma_err()
186 int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigne argument
77 dwmac5_handle_mac_err(struct net_device *ndev, void __iomem *ioaddr, bool correctable, struct stmmac_safety_stats *stats) dwmac5_handle_mac_err() argument
125 dwmac5_handle_mtl_err(struct net_device *ndev, void __iomem *ioaddr, bool correctable, struct stmmac_safety_stats *stats) dwmac5_handle_mtl_err() argument
173 dwmac5_handle_dma_err(struct net_device *ndev, void __iomem *ioaddr, bool correctable, struct stmmac_safety_stats *stats) dwmac5_handle_dma_err() argument
242 dwmac5_safety_feat_irq_status(struct net_device *ndev, void __iomem *ioaddr, unsigned int asp, struct stmmac_safety_stats *stats) dwmac5_safety_feat_irq_status() argument
305 dwmac5_rxp_disable(void __iomem *ioaddr) dwmac5_rxp_disable() argument
321 dwmac5_rxp_enable(void __iomem *ioaddr) dwmac5_rxp_enable() argument
330 dwmac5_rxp_update_single_entry(void __iomem *ioaddr, struct stmmac_tc_entry *entry, int pos) dwmac5_rxp_update_single_entry() argument
412 dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries, unsigned int count) dwmac5_rxp_config() argument
499 dwmac5_flex_pps_config(void __iomem *ioaddr, int index, struct stmmac_pps_cfg *cfg, bool enable, u32 sub_second_inc, u32 systime_flags) dwmac5_flex_pps_config() argument
555 dwmac5_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl) dwmac5_est_write() argument
573 dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg, unsigned int ptp_rate) dwmac5_est_configure() argument
606 dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num_rxq, bool enable) dwmac5_fpe_configure() argument
[all...]
H A Ddwmac4_dma.c17 static void dwmac4_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) in dwmac4_dma_axi() argument
19 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); in dwmac4_dma_axi()
68 writel(value, ioaddr + DMA_SYS_BUS_MODE); in dwmac4_dma_axi()
71 static void dwmac4_dma_init_rx_chan(void __iomem *ioaddr, in dwmac4_dma_init_rx_chan() argument
78 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_init_rx_chan()
80 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_init_rx_chan()
84 ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(chan)); in dwmac4_dma_init_rx_chan()
86 writel(lower_32_bits(dma_rx_phy), ioaddr + DMA_CHAN_RX_BASE_ADDR(chan)); in dwmac4_dma_init_rx_chan()
89 static void dwmac4_dma_init_tx_chan(void __iomem *ioaddr, in dwmac4_dma_init_tx_chan() argument
96 value = readl(ioaddr in dwmac4_dma_init_tx_chan()
111 dwmac4_dma_init_channel(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, u32 chan) dwmac4_dma_init_channel() argument
127 dwmac410_dma_init_channel(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, u32 chan) dwmac410_dma_init_channel() argument
144 dwmac4_dma_init(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, int atds) dwmac4_dma_init() argument
166 _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel, u32 *reg_space) _dwmac4_dump_dma_regs() argument
205 dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space) dwmac4_dump_dma_regs() argument
213 dwmac4_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 number_chan) dwmac4_rx_watchdog() argument
221 dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, u32 channel, int fifosz, u8 qmode) dwmac4_dma_rx_chan_op_mode() argument
288 dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode, u32 channel, int fifosz, u8 qmode) dwmac4_dma_tx_chan_op_mode() argument
340 dwmac4_get_hw_feature(void __iomem *ioaddr, struct dma_features *dma_cap) dwmac4_get_hw_feature() argument
433 dwmac4_enable_tso(void __iomem *ioaddr, bool en, u32 chan) dwmac4_enable_tso() argument
450 dwmac4_qmode(void __iomem *ioaddr, u32 channel, u8 qmode) dwmac4_qmode() argument
463 dwmac4_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan) dwmac4_set_bfsize() argument
473 dwmac4_enable_sph(void __iomem *ioaddr, bool en, u32 chan) dwmac4_enable_sph() argument
489 dwmac4_enable_tbs(void __iomem *ioaddr, bool en, u32 chan) dwmac4_enable_tbs() argument
[all...]
H A Ddwmac_lib.c16 int dwmac_dma_reset(void __iomem *ioaddr) in dwmac_dma_reset() argument
18 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac_dma_reset()
22 writel(value, ioaddr + DMA_BUS_MODE); in dwmac_dma_reset()
24 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, in dwmac_dma_reset()
30 void dwmac_enable_dma_transmission(void __iomem *ioaddr) in dwmac_enable_dma_transmission() argument
32 writel(1, ioaddr + DMA_XMT_POLL_DEMAND); in dwmac_enable_dma_transmission()
35 void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) in dwmac_enable_dma_irq() argument
37 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_enable_dma_irq()
44 writel(value, ioaddr + DMA_INTR_ENA); in dwmac_enable_dma_irq()
47 void dwmac_disable_dma_irq(void __iomem *ioaddr, u3 argument
59 dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) dwmac_dma_start_tx() argument
66 dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) dwmac_dma_stop_tx() argument
73 dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) dwmac_dma_start_rx() argument
80 dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) dwmac_dma_stop_rx() argument
157 dwmac_dma_interrupt(void __iomem *ioaddr, struct stmmac_extra_stats *x, u32 chan) dwmac_dma_interrupt() argument
228 dwmac_dma_flush_tx_fifo(void __iomem *ioaddr) dwmac_dma_flush_tx_fifo() argument
236 stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6], unsigned int high, unsigned int low) stmmac_set_mac_addr() argument
253 stmmac_set_mac(void __iomem *ioaddr, bool enable) stmmac_set_mac() argument
265 stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, unsigned int high, unsigned int low) stmmac_get_mac_addr() argument
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/stmicro/stmmac/
H A Ddwxgmac2_dma.c11 static int dwxgmac2_dma_reset(void __iomem *ioaddr) in dwxgmac2_dma_reset() argument
13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value, in dwxgmac2_dma_reset()
22 static void dwxgmac2_dma_init(void __iomem *ioaddr, in dwxgmac2_dma_init() argument
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
33 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
37 void __iomem *ioaddr, in dwxgmac2_dma_init_chan()
40 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan()
45 writel(value, ioaddr in dwxgmac2_dma_init_chan()
36 dwxgmac2_dma_init_chan(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, u32 chan) dwxgmac2_dma_init_chan() argument
49 dwxgmac2_dma_init_rx_chan(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, dma_addr_t phy, u32 chan) dwxgmac2_dma_init_rx_chan() argument
66 dwxgmac2_dma_init_tx_chan(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, dma_addr_t phy, u32 chan) dwxgmac2_dma_init_tx_chan() argument
84 dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) dwxgmac2_dma_axi() argument
137 dwxgmac2_dma_dump_regs(struct stmmac_priv *priv, void __iomem *ioaddr, u32 *reg_space) dwxgmac2_dma_dump_regs() argument
146 dwxgmac2_dma_rx_mode(struct stmmac_priv *priv, void __iomem *ioaddr, int mode, u32 channel, int fifosz, u8 qmode) dwxgmac2_dma_rx_mode() argument
212 dwxgmac2_dma_tx_mode(struct stmmac_priv *priv, void __iomem *ioaddr, int mode, u32 channel, int fifosz, u8 qmode) dwxgmac2_dma_tx_mode() argument
255 dwxgmac2_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx) dwxgmac2_enable_dma_irq() argument
269 dwxgmac2_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx) dwxgmac2_disable_dma_irq() argument
283 dwxgmac2_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) dwxgmac2_dma_start_tx() argument
297 dwxgmac2_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) dwxgmac2_dma_stop_tx() argument
311 dwxgmac2_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) dwxgmac2_dma_start_rx() argument
325 dwxgmac2_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) dwxgmac2_dma_stop_rx() argument
335 dwxgmac2_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_extra_stats *x, u32 chan, u32 dir) dwxgmac2_dma_interrupt() argument
388 dwxgmac2_get_hw_feature(void __iomem *ioaddr, struct dma_features *dma_cap) dwxgmac2_get_hw_feature() argument
503 dwxgmac2_rx_watchdog(struct stmmac_priv *priv, void __iomem *ioaddr, u32 riwt, u32 queue) dwxgmac2_rx_watchdog() argument
509 dwxgmac2_set_rx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr, u32 len, u32 chan) dwxgmac2_set_rx_ring_len() argument
515 dwxgmac2_set_tx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr, u32 len, u32 chan) dwxgmac2_set_tx_ring_len() argument
521 dwxgmac2_set_rx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr, u32 ptr, u32 chan) dwxgmac2_set_rx_tail_ptr() argument
527 dwxgmac2_set_tx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr, u32 ptr, u32 chan) dwxgmac2_set_tx_tail_ptr() argument
533 dwxgmac2_enable_tso(struct stmmac_priv *priv, void __iomem *ioaddr, bool en, u32 chan) dwxgmac2_enable_tso() argument
546 dwxgmac2_qmode(struct stmmac_priv *priv, void __iomem *ioaddr, u32 channel, u8 qmode) dwxgmac2_qmode() argument
564 dwxgmac2_set_bfsize(struct stmmac_priv *priv, void __iomem *ioaddr, int bfsize, u32 chan) dwxgmac2_set_bfsize() argument
575 dwxgmac2_enable_sph(struct stmmac_priv *priv, void __iomem *ioaddr, bool en, u32 chan) dwxgmac2_enable_sph() argument
592 dwxgmac2_enable_tbs(struct stmmac_priv *priv, void __iomem *ioaddr, bool en, u32 chan) dwxgmac2_enable_tbs() argument
[all...]
H A Ddwmac5.c78 void __iomem *ioaddr, bool correctable, in dwmac5_handle_mac_err()
83 value = readl(ioaddr + MAC_DPP_FSM_INT_STATUS); in dwmac5_handle_mac_err()
84 writel(value, ioaddr + MAC_DPP_FSM_INT_STATUS); in dwmac5_handle_mac_err()
126 void __iomem *ioaddr, bool correctable, in dwmac5_handle_mtl_err()
131 value = readl(ioaddr + MTL_ECC_INT_STATUS); in dwmac5_handle_mtl_err()
132 writel(value, ioaddr + MTL_ECC_INT_STATUS); in dwmac5_handle_mtl_err()
174 void __iomem *ioaddr, bool correctable, in dwmac5_handle_dma_err()
179 value = readl(ioaddr + DMA_ECC_INT_STATUS); in dwmac5_handle_dma_err()
180 writel(value, ioaddr + DMA_ECC_INT_STATUS); in dwmac5_handle_dma_err()
186 int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigne argument
77 dwmac5_handle_mac_err(struct net_device *ndev, void __iomem *ioaddr, bool correctable, struct stmmac_safety_stats *stats) dwmac5_handle_mac_err() argument
125 dwmac5_handle_mtl_err(struct net_device *ndev, void __iomem *ioaddr, bool correctable, struct stmmac_safety_stats *stats) dwmac5_handle_mtl_err() argument
173 dwmac5_handle_dma_err(struct net_device *ndev, void __iomem *ioaddr, bool correctable, struct stmmac_safety_stats *stats) dwmac5_handle_dma_err() argument
267 dwmac5_safety_feat_irq_status(struct net_device *ndev, void __iomem *ioaddr, unsigned int asp, struct stmmac_safety_stats *stats) dwmac5_safety_feat_irq_status() argument
330 dwmac5_rxp_disable(void __iomem *ioaddr) dwmac5_rxp_disable() argument
342 dwmac5_rxp_enable(void __iomem *ioaddr) dwmac5_rxp_enable() argument
351 dwmac5_rxp_update_single_entry(void __iomem *ioaddr, struct stmmac_tc_entry *entry, int pos) dwmac5_rxp_update_single_entry() argument
433 dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries, unsigned int count) dwmac5_rxp_config() argument
520 dwmac5_flex_pps_config(void __iomem *ioaddr, int index, struct stmmac_pps_cfg *cfg, bool enable, u32 sub_second_inc, u32 systime_flags) dwmac5_flex_pps_config() argument
576 dwmac5_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl) dwmac5_est_write() argument
594 dwmac5_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg, unsigned int ptp_rate) dwmac5_est_configure() argument
636 dwmac5_est_irq_status(void __iomem *ioaddr, struct net_device *dev, struct stmmac_extra_stats *x, u32 txqcnt) dwmac5_est_irq_status() argument
713 dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, u32 num_txq, u32 num_rxq, bool enable) dwmac5_fpe_configure() argument
731 dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev) dwmac5_fpe_irq_status() argument
766 dwmac5_fpe_send_mpacket(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, enum stmmac_mpacket_type type) dwmac5_fpe_send_mpacket() argument
[all...]
H A Ddwmac4_lib.c16 int dwmac4_dma_reset(void __iomem *ioaddr) in dwmac4_dma_reset() argument
18 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset()
22 writel(value, ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset()
24 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, in dwmac4_dma_reset()
29 void dwmac4_set_rx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr, in dwmac4_set_rx_tail_ptr() argument
34 writel(tail_ptr, ioaddr + DMA_CHAN_RX_END_ADDR(dwmac4_addrs, chan)); in dwmac4_set_rx_tail_ptr()
37 void dwmac4_set_tx_tail_ptr(struct stmmac_priv *priv, void __iomem *ioaddr, in dwmac4_set_tx_tail_ptr() argument
42 writel(tail_ptr, ioaddr + DMA_CHAN_TX_END_ADDR(dwmac4_addrs, chan)); in dwmac4_set_tx_tail_ptr()
45 void dwmac4_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr, in dwmac4_dma_start_tx() argument
49 u32 value = readl(ioaddr in dwmac4_dma_start_tx()
59 dwmac4_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) dwmac4_dma_stop_tx() argument
70 dwmac4_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) dwmac4_dma_start_rx() argument
86 dwmac4_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) dwmac4_dma_stop_rx() argument
96 dwmac4_set_tx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr, u32 len, u32 chan) dwmac4_set_tx_ring_len() argument
104 dwmac4_set_rx_ring_len(struct stmmac_priv *priv, void __iomem *ioaddr, u32 len, u32 chan) dwmac4_set_rx_ring_len() argument
112 dwmac4_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx) dwmac4_enable_dma_irq() argument
126 dwmac410_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx) dwmac410_enable_dma_irq() argument
140 dwmac4_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx) dwmac4_disable_dma_irq() argument
154 dwmac410_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan, bool rx, bool tx) dwmac410_disable_dma_irq() argument
168 dwmac4_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_extra_stats *x, u32 chan, u32 dir) dwmac4_dma_interrupt() argument
225 stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], unsigned int high, unsigned int low) stmmac_dwmac4_set_mac_addr() argument
242 stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable) stmmac_dwmac4_set_mac() argument
256 stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, unsigned int high, unsigned int low) stmmac_dwmac4_get_mac_addr() argument
[all...]
H A Ddwmac_lib.c17 int dwmac_dma_reset(void __iomem *ioaddr) in dwmac_dma_reset() argument
19 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac_dma_reset()
23 writel(value, ioaddr + DMA_BUS_MODE); in dwmac_dma_reset()
25 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, in dwmac_dma_reset()
31 void dwmac_enable_dma_transmission(void __iomem *ioaddr) in dwmac_enable_dma_transmission() argument
33 writel(1, ioaddr + DMA_XMT_POLL_DEMAND); in dwmac_enable_dma_transmission()
36 void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, in dwmac_enable_dma_irq() argument
39 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_enable_dma_irq()
46 writel(value, ioaddr + DMA_INTR_ENA); in dwmac_enable_dma_irq()
49 void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, in dwmac_disable_dma_irq() argument
62 dwmac_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) dwmac_dma_start_tx() argument
70 dwmac_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) dwmac_dma_stop_tx() argument
77 dwmac_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) dwmac_dma_start_rx() argument
85 dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, u32 chan) dwmac_dma_stop_rx() argument
162 dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_extra_stats *x, u32 chan, u32 dir) dwmac_dma_interrupt() argument
243 dwmac_dma_flush_tx_fifo(void __iomem *ioaddr) dwmac_dma_flush_tx_fifo() argument
251 stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], unsigned int high, unsigned int low) stmmac_set_mac_addr() argument
268 stmmac_set_mac(void __iomem *ioaddr, bool enable) stmmac_set_mac() argument
284 stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, unsigned int high, unsigned int low) stmmac_get_mac_addr() argument
[all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/smsc/
H A Dsmc9194.c268 static int smc_probe(struct net_device *dev, int ioaddr);
290 static void smc_reset( int ioaddr );
293 static void smc_enable( int ioaddr );
296 static void smc_shutdown( int ioaddr );
300 static int smc_findirq( int ioaddr );
303 . Function: smc_reset( int ioaddr )
319 static void smc_reset( int ioaddr ) in smc_reset()
324 outw( RCR_SOFTRESET, ioaddr + RCR ); in smc_reset()
331 outw( RCR_CLEAR, ioaddr + RCR ); in smc_reset()
332 outw( TCR_CLEAR, ioaddr in smc_reset()
421 smc_setmulticast(int ioaddr, struct net_device *dev) smc_setmulticast() argument
471 unsigned int ioaddr = dev->base_addr; smc_wait_to_send_packet() local
584 unsigned int ioaddr; smc_hardware_send_packet() local
739 smc_findirq(int ioaddr) smc_findirq() argument
845 smc_probe(struct net_device *dev, int ioaddr) smc_probe() argument
1048 int ioaddr = dev->base_addr; smc_open() local
1126 int ioaddr = dev->base_addr; smc_rcv() local
1247 int ioaddr = dev->base_addr; smc_tx() local
1312 int ioaddr = dev->base_addr; smc_interrupt() local
1452 short ioaddr = dev->base_addr; smc_set_multicast_list() local
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/smsc/
H A Dsmc9194.c268 static int smc_probe(struct net_device *dev, int ioaddr);
290 static void smc_reset( int ioaddr );
293 static void smc_enable( int ioaddr );
296 static void smc_shutdown( int ioaddr );
300 static int smc_findirq( int ioaddr );
303 . Function: smc_reset( int ioaddr )
319 static void smc_reset( int ioaddr ) in smc_reset()
324 outw( RCR_SOFTRESET, ioaddr + RCR ); in smc_reset()
331 outw( RCR_CLEAR, ioaddr + RCR ); in smc_reset()
332 outw( TCR_CLEAR, ioaddr in smc_reset()
421 smc_setmulticast(int ioaddr, struct net_device *dev) smc_setmulticast() argument
471 unsigned int ioaddr = dev->base_addr; smc_wait_to_send_packet() local
584 unsigned int ioaddr; smc_hardware_send_packet() local
739 smc_findirq(int ioaddr) smc_findirq() argument
845 smc_probe(struct net_device *dev, int ioaddr) smc_probe() argument
1050 int ioaddr = dev->base_addr; smc_open() local
1128 int ioaddr = dev->base_addr; smc_rcv() local
1249 int ioaddr = dev->base_addr; smc_tx() local
1314 int ioaddr = dev->base_addr; smc_interrupt() local
1454 short ioaddr = dev->base_addr; smc_set_multicast_list() local
[all...]
/kernel/linux/linux-5.10/drivers/net/arcnet/
H A Dcom90io.c73 int ioaddr = dev->base_addr; in get_buffer_byte() local
75 arcnet_outb(offset >> 8, ioaddr, COM9026_REG_W_ADDR_HI); in get_buffer_byte()
76 arcnet_outb(offset & 0xff, ioaddr, COM9026_REG_W_ADDR_LO); in get_buffer_byte()
78 return arcnet_inb(ioaddr, COM9026_REG_RW_MEMDATA); in get_buffer_byte()
85 int ioaddr = dev->base_addr; in put_buffer_byte() local
87 arcnet_outb(offset >> 8, ioaddr, COM9026_REG_W_ADDR_HI); in put_buffer_byte()
88 arcnet_outb(offset & 0xff, ioaddr, COM9026_REG_W_ADDR_LO); in put_buffer_byte()
90 arcnet_outb(datum, ioaddr, COM9026_REG_RW_MEMDATA); in put_buffer_byte()
98 int ioaddr = dev->base_addr; in get_whole_buffer() local
100 arcnet_outb((offset >> 8) | AUTOINCflag, ioaddr, COM9026_REG_W_ADDR_H in get_whole_buffer()
114 int ioaddr = dev->base_addr; put_whole_buffer() local
132 int ioaddr = dev->base_addr, status; com90io_probe() local
224 int ioaddr = dev->base_addr; com90io_found() local
282 short ioaddr = dev->base_addr; com90io_reset() local
313 short ioaddr = dev->base_addr; com90io_command() local
320 short ioaddr = dev->base_addr; com90io_status() local
327 short ioaddr = dev->base_addr; com90io_setmask() local
410 int ioaddr = dev->base_addr; com90io_exit() local
[all...]
/kernel/linux/linux-6.6/drivers/net/arcnet/
H A Dcom90io.c73 int ioaddr = dev->base_addr; in get_buffer_byte() local
75 arcnet_outb(offset >> 8, ioaddr, COM9026_REG_W_ADDR_HI); in get_buffer_byte()
76 arcnet_outb(offset & 0xff, ioaddr, COM9026_REG_W_ADDR_LO); in get_buffer_byte()
78 return arcnet_inb(ioaddr, COM9026_REG_RW_MEMDATA); in get_buffer_byte()
85 int ioaddr = dev->base_addr; in put_buffer_byte() local
87 arcnet_outb(offset >> 8, ioaddr, COM9026_REG_W_ADDR_HI); in put_buffer_byte()
88 arcnet_outb(offset & 0xff, ioaddr, COM9026_REG_W_ADDR_LO); in put_buffer_byte()
90 arcnet_outb(datum, ioaddr, COM9026_REG_RW_MEMDATA); in put_buffer_byte()
98 int ioaddr = dev->base_addr; in get_whole_buffer() local
100 arcnet_outb((offset >> 8) | AUTOINCflag, ioaddr, COM9026_REG_W_ADDR_H in get_whole_buffer()
114 int ioaddr = dev->base_addr; put_whole_buffer() local
132 int ioaddr = dev->base_addr, status; com90io_probe() local
224 int ioaddr = dev->base_addr; com90io_found() local
282 short ioaddr = dev->base_addr; com90io_reset() local
313 short ioaddr = dev->base_addr; com90io_command() local
320 short ioaddr = dev->base_addr; com90io_status() local
327 short ioaddr = dev->base_addr; com90io_setmask() local
410 int ioaddr = dev->base_addr; com90io_exit() local
[all...]
/kernel/linux/linux-5.10/drivers/net/ethernet/realtek/
H A Datp.c193 static int atp_probe1(long ioaddr);
195 static unsigned short eeprom_op(long ioaddr, unsigned int cmd);
198 static void write_packet(long ioaddr, int length, unsigned char *packet, int pad, int mode);
199 static void trigger_send(long ioaddr, int length);
204 static void read_block(long ioaddr, int length, unsigned char *buffer, int data_mode);
232 long ioaddr = *port; in atp_init() local
233 outb(0x57, ioaddr + PAR_DATA); in atp_init()
234 if (inb(ioaddr + PAR_DATA) != 0x57) in atp_init()
236 if (atp_probe1(ioaddr) == 0) in atp_init()
253 static int __init atp_probe1(long ioaddr) in atp_probe1() argument
370 long ioaddr = dev->base_addr; get_node_ID() local
400 eeprom_op(long ioaddr, u32 cmd) eeprom_op() argument
456 long ioaddr = dev->base_addr; hardware_init() local
489 trigger_send(long ioaddr, int length) trigger_send() argument
496 write_packet(long ioaddr, int length, unsigned char *packet, int pad_len, int data_mode) write_packet() argument
538 long ioaddr = dev->base_addr; tx_timeout() local
555 long ioaddr = dev->base_addr; atp_send_packet() local
596 long ioaddr; atp_interrupt() local
720 long ioaddr = dev->base_addr; atp_timed_checker() local
757 long ioaddr = dev->base_addr; net_rx() local
803 read_block(long ioaddr, int length, unsigned char *p, int data_mode) read_block() argument
829 long ioaddr = dev->base_addr; net_close() local
855 long ioaddr = dev->base_addr; set_rx_mode() local
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/realtek/
H A Datp.c193 static int atp_probe1(long ioaddr);
195 static unsigned short eeprom_op(long ioaddr, unsigned int cmd);
198 static void write_packet(long ioaddr, int length, unsigned char *packet, int pad, int mode);
199 static void trigger_send(long ioaddr, int length);
204 static void read_block(long ioaddr, int length, unsigned char *buffer, int data_mode);
232 long ioaddr = *port; in atp_init() local
233 outb(0x57, ioaddr + PAR_DATA); in atp_init()
234 if (inb(ioaddr + PAR_DATA) != 0x57) in atp_init()
236 if (atp_probe1(ioaddr) == 0) in atp_init()
253 static int __init atp_probe1(long ioaddr) in atp_probe1() argument
370 long ioaddr = dev->base_addr; get_node_ID() local
402 eeprom_op(long ioaddr, u32 cmd) eeprom_op() argument
458 long ioaddr = dev->base_addr; hardware_init() local
491 trigger_send(long ioaddr, int length) trigger_send() argument
498 write_packet(long ioaddr, int length, unsigned char *packet, int pad_len, int data_mode) write_packet() argument
540 long ioaddr = dev->base_addr; tx_timeout() local
557 long ioaddr = dev->base_addr; atp_send_packet() local
598 long ioaddr; atp_interrupt() local
722 long ioaddr = dev->base_addr; atp_timed_checker() local
759 long ioaddr = dev->base_addr; net_rx() local
805 read_block(long ioaddr, int length, unsigned char *p, int data_mode) read_block() argument
831 long ioaddr = dev->base_addr; net_close() local
857 long ioaddr = dev->base_addr; set_rx_mode() local
[all...]
/kernel/linux/linux-5.10/drivers/net/
H A Dsb1000.c89 static int card_wait_for_busy_clear(const int ioaddr[],
91 static int card_wait_for_ready(const int ioaddr[], const char* name,
93 static int card_send_command(const int ioaddr[], const char* name,
97 static int sb1000_wait_for_ready(const int ioaddr[], const char* name);
98 static int sb1000_wait_for_ready_clear(const int ioaddr[],
100 static void sb1000_send_command(const int ioaddr[], const char* name,
102 static void sb1000_read_status(const int ioaddr[], unsigned char in[]);
103 static void sb1000_issue_read_command(const int ioaddr[],
107 static int sb1000_reset(const int ioaddr[], const char* name);
108 static int sb1000_check_CRC(const int ioaddr[], cons
148 unsigned short ioaddr[2], irq; sb1000_probe_one() local
257 card_wait_for_busy_clear(const int ioaddr[], const char* name) card_wait_for_busy_clear() argument
281 card_wait_for_ready(const int ioaddr[], const char* name, unsigned char in[]) card_wait_for_ready() argument
312 card_send_command(const int ioaddr[], const char* name, const unsigned char out[], unsigned char in[]) card_send_command() argument
359 sb1000_wait_for_ready(const int ioaddr[], const char* name) sb1000_wait_for_ready() argument
385 sb1000_wait_for_ready_clear(const int ioaddr[], const char* name) sb1000_wait_for_ready_clear() argument
410 sb1000_send_command(const int ioaddr[], const char* name, const unsigned char out[]) sb1000_send_command() argument
426 sb1000_read_status(const int ioaddr[], unsigned char in[]) sb1000_read_status() argument
437 sb1000_issue_read_command(const int ioaddr[], const char* name) sb1000_issue_read_command() argument
452 sb1000_reset(const int ioaddr[], const char* name) sb1000_reset() argument
482 sb1000_check_CRC(const int ioaddr[], const char* name) sb1000_check_CRC() argument
498 sb1000_start_get_set_command(const int ioaddr[], const char* name) sb1000_start_get_set_command() argument
508 sb1000_end_get_set_command(const int ioaddr[], const char* name) sb1000_end_get_set_command() argument
522 sb1000_activate(const int ioaddr[], const char* name) sb1000_activate() argument
549 sb1000_get_firmware_version(const int ioaddr[], const char* name, unsigned char version[], int do_end) sb1000_get_firmware_version() argument
573 sb1000_get_frequency(const int ioaddr[], const char* name, int* frequency) sb1000_get_frequency() argument
591 sb1000_set_frequency(const int ioaddr[], const char* name, int frequency) sb1000_set_frequency() argument
621 sb1000_get_PIDs(const int ioaddr[], const char* name, short PID[]) sb1000_get_PIDs() argument
656 sb1000_set_PIDs(const int ioaddr[], const char* name, const short PID[]) sb1000_set_PIDs() argument
743 int ioaddr, ns; sb1000_rx() local
905 int ioaddr[2]; sb1000_error_dpc() local
930 int ioaddr[2], status; sb1000_open() local
995 int ioaddr[2], status, frequency; sb1000_dev_ioctl() local
1092 int ioaddr[2]; sb1000_interrupt() local
1143 int ioaddr[2]; sb1000_close() local
[all...]
/kernel/linux/linux-6.6/drivers/net/
H A Dsb1000.c90 static int card_wait_for_busy_clear(const int ioaddr[],
92 static int card_wait_for_ready(const int ioaddr[], const char* name,
94 static int card_send_command(const int ioaddr[], const char* name,
98 static int sb1000_wait_for_ready(const int ioaddr[], const char* name);
99 static int sb1000_wait_for_ready_clear(const int ioaddr[],
101 static void sb1000_send_command(const int ioaddr[], const char* name,
103 static void sb1000_read_status(const int ioaddr[], unsigned char in[]);
104 static void sb1000_issue_read_command(const int ioaddr[],
108 static int sb1000_reset(const int ioaddr[], const char* name);
109 static int sb1000_check_CRC(const int ioaddr[], cons
149 unsigned short ioaddr[2], irq; sb1000_probe_one() local
262 card_wait_for_busy_clear(const int ioaddr[], const char* name) card_wait_for_busy_clear() argument
286 card_wait_for_ready(const int ioaddr[], const char* name, unsigned char in[]) card_wait_for_ready() argument
317 card_send_command(const int ioaddr[], const char* name, const unsigned char out[], unsigned char in[]) card_send_command() argument
364 sb1000_wait_for_ready(const int ioaddr[], const char* name) sb1000_wait_for_ready() argument
390 sb1000_wait_for_ready_clear(const int ioaddr[], const char* name) sb1000_wait_for_ready_clear() argument
415 sb1000_send_command(const int ioaddr[], const char* name, const unsigned char out[]) sb1000_send_command() argument
431 sb1000_read_status(const int ioaddr[], unsigned char in[]) sb1000_read_status() argument
442 sb1000_issue_read_command(const int ioaddr[], const char* name) sb1000_issue_read_command() argument
457 sb1000_reset(const int ioaddr[], const char* name) sb1000_reset() argument
487 sb1000_check_CRC(const int ioaddr[], const char* name) sb1000_check_CRC() argument
503 sb1000_start_get_set_command(const int ioaddr[], const char* name) sb1000_start_get_set_command() argument
513 sb1000_end_get_set_command(const int ioaddr[], const char* name) sb1000_end_get_set_command() argument
527 sb1000_activate(const int ioaddr[], const char* name) sb1000_activate() argument
554 sb1000_get_firmware_version(const int ioaddr[], const char* name, unsigned char version[], int do_end) sb1000_get_firmware_version() argument
578 sb1000_get_frequency(const int ioaddr[], const char* name, int* frequency) sb1000_get_frequency() argument
596 sb1000_set_frequency(const int ioaddr[], const char* name, int frequency) sb1000_set_frequency() argument
626 sb1000_get_PIDs(const int ioaddr[], const char* name, short PID[]) sb1000_get_PIDs() argument
661 sb1000_set_PIDs(const int ioaddr[], const char* name, const short PID[]) sb1000_set_PIDs() argument
748 int ioaddr, ns; sb1000_rx() local
910 int ioaddr[2]; sb1000_error_dpc() local
935 int ioaddr[2], status; sb1000_open() local
1001 int ioaddr[2], status, frequency; sb1000_siocdevprivate() local
1098 int ioaddr[2]; sb1000_interrupt() local
1149 int ioaddr[2]; sb1000_close() local
[all...]
/kernel/linux/linux-5.10/drivers/rtc/
H A Drtc-ds1742.c59 void __iomem *ioaddr = pdata->ioaddr_rtc; in ds1742_rtc_set_time() local
64 writeb(RTC_WRITE, ioaddr + RTC_CONTROL); in ds1742_rtc_set_time()
66 writeb(bin2bcd(tm->tm_year % 100), ioaddr + RTC_YEAR); in ds1742_rtc_set_time()
67 writeb(bin2bcd(tm->tm_mon + 1), ioaddr + RTC_MONTH); in ds1742_rtc_set_time()
68 writeb(bin2bcd(tm->tm_wday) & RTC_DAY_MASK, ioaddr + RTC_DAY); in ds1742_rtc_set_time()
69 writeb(bin2bcd(tm->tm_mday), ioaddr + RTC_DATE); in ds1742_rtc_set_time()
70 writeb(bin2bcd(tm->tm_hour), ioaddr + RTC_HOURS); in ds1742_rtc_set_time()
71 writeb(bin2bcd(tm->tm_min), ioaddr + RTC_MINUTES); in ds1742_rtc_set_time()
72 writeb(bin2bcd(tm->tm_sec) & RTC_SECONDS_MASK, ioaddr + RTC_SECONDS); in ds1742_rtc_set_time()
75 writeb(RTC_WRITE | (century & RTC_CENTURY_MASK), ioaddr in ds1742_rtc_set_time()
83 void __iomem *ioaddr = pdata->ioaddr_rtc; ds1742_rtc_read_time() local
122 void __iomem *ioaddr = pdata->ioaddr_nvram; ds1742_nvram_read() local
134 void __iomem *ioaddr = pdata->ioaddr_nvram; ds1742_nvram_write() local
148 void __iomem *ioaddr; ds1742_rtc_probe() local
[all...]
/kernel/linux/linux-6.6/drivers/rtc/
H A Drtc-ds1742.c58 void __iomem *ioaddr = pdata->ioaddr_rtc; in ds1742_rtc_set_time() local
63 writeb(RTC_WRITE, ioaddr + RTC_CONTROL); in ds1742_rtc_set_time()
65 writeb(bin2bcd(tm->tm_year % 100), ioaddr + RTC_YEAR); in ds1742_rtc_set_time()
66 writeb(bin2bcd(tm->tm_mon + 1), ioaddr + RTC_MONTH); in ds1742_rtc_set_time()
67 writeb(bin2bcd(tm->tm_wday) & RTC_DAY_MASK, ioaddr + RTC_DAY); in ds1742_rtc_set_time()
68 writeb(bin2bcd(tm->tm_mday), ioaddr + RTC_DATE); in ds1742_rtc_set_time()
69 writeb(bin2bcd(tm->tm_hour), ioaddr + RTC_HOURS); in ds1742_rtc_set_time()
70 writeb(bin2bcd(tm->tm_min), ioaddr + RTC_MINUTES); in ds1742_rtc_set_time()
71 writeb(bin2bcd(tm->tm_sec) & RTC_SECONDS_MASK, ioaddr + RTC_SECONDS); in ds1742_rtc_set_time()
74 writeb(RTC_WRITE | (century & RTC_CENTURY_MASK), ioaddr in ds1742_rtc_set_time()
82 void __iomem *ioaddr = pdata->ioaddr_rtc; ds1742_rtc_read_time() local
121 void __iomem *ioaddr = pdata->ioaddr_nvram; ds1742_nvram_read() local
133 void __iomem *ioaddr = pdata->ioaddr_nvram; ds1742_nvram_write() local
147 void __iomem *ioaddr; ds1742_rtc_probe() local
[all...]

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