| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vega10_ih.c | 49 struct amdgpu_ih_regs *ih_regs; in vega10_ih_init_register_offset() local
52 ih_regs = &adev->irq.ih.ih_regs; in vega10_ih_init_register_offset()
53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega10_ih_init_register_offset()
54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in vega10_ih_init_register_offset()
55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_init_register_offset()
56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega10_ih_init_register_offset()
57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega10_ih_init_register_offset()
58 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); in vega10_ih_init_register_offset()
59 ih_regs in vega10_ih_init_register_offset()
100 struct amdgpu_ih_regs *ih_regs; vega10_ih_toggle_ring_interrupts() local
211 struct amdgpu_ih_regs *ih_regs; vega10_ih_enable_ring() local
339 struct amdgpu_ih_regs *ih_regs; vega10_ih_get_wptr() local
398 struct amdgpu_ih_regs *ih_regs; vega10_ih_irq_rearm() local
422 struct amdgpu_ih_regs *ih_regs; vega10_ih_set_rptr() local
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| H A D | navi10_ih.c | 51 struct amdgpu_ih_regs *ih_regs; in navi10_ih_init_register_offset() local
54 ih_regs = &adev->irq.ih.ih_regs; in navi10_ih_init_register_offset()
55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in navi10_ih_init_register_offset()
56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in navi10_ih_init_register_offset()
57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in navi10_ih_init_register_offset()
58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in navi10_ih_init_register_offset()
59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in navi10_ih_init_register_offset()
60 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); in navi10_ih_init_register_offset()
61 ih_regs in navi10_ih_init_register_offset()
156 struct amdgpu_ih_regs *ih_regs; navi10_ih_toggle_ring_interrupts() local
266 struct amdgpu_ih_regs *ih_regs; navi10_ih_enable_ring() local
410 struct amdgpu_ih_regs *ih_regs; navi10_ih_get_wptr() local
467 struct amdgpu_ih_regs *ih_regs; navi10_ih_irq_rearm() local
492 struct amdgpu_ih_regs *ih_regs; navi10_ih_set_rptr() local
[all...] |
| H A D | vega20_ih.c | 57 struct amdgpu_ih_regs *ih_regs; in vega20_ih_init_register_offset() local
60 ih_regs = &adev->irq.ih.ih_regs; in vega20_ih_init_register_offset()
61 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega20_ih_init_register_offset()
62 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in vega20_ih_init_register_offset()
63 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega20_ih_init_register_offset()
64 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega20_ih_init_register_offset()
65 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega20_ih_init_register_offset()
66 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); in vega20_ih_init_register_offset()
67 ih_regs in vega20_ih_init_register_offset()
108 struct amdgpu_ih_regs *ih_regs; vega20_ih_toggle_ring_interrupts() local
220 struct amdgpu_ih_regs *ih_regs; vega20_ih_enable_ring() local
387 struct amdgpu_ih_regs *ih_regs; vega20_ih_get_wptr() local
446 struct amdgpu_ih_regs *ih_regs; vega20_ih_irq_rearm() local
471 struct amdgpu_ih_regs *ih_regs; vega20_ih_set_rptr() local
[all...] |
| H A D | ih_v6_0.c | 48 struct amdgpu_ih_regs *ih_regs; in ih_v6_0_init_register_offset() local
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_0_init_register_offset()
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); in ih_v6_0_init_register_offset()
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI); in ih_v6_0_init_register_offset()
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); in ih_v6_0_init_register_offset()
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v6_0_init_register_offset()
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v6_0_init_register_offset()
59 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR); in ih_v6_0_init_register_offset()
60 ih_regs in ih_v6_0_init_register_offset()
131 struct amdgpu_ih_regs *ih_regs; ih_v6_0_toggle_ring_interrupts() local
240 struct amdgpu_ih_regs *ih_regs; ih_v6_0_enable_ring() local
395 struct amdgpu_ih_regs *ih_regs; ih_v6_0_get_wptr() local
443 struct amdgpu_ih_regs *ih_regs; ih_v6_0_irq_rearm() local
468 struct amdgpu_ih_regs *ih_regs; ih_v6_0_set_rptr() local
[all...] |
| H A D | ih_v6_1.c | 48 struct amdgpu_ih_regs *ih_regs; in ih_v6_1_init_register_offset() local
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_1_init_register_offset()
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); in ih_v6_1_init_register_offset()
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI); in ih_v6_1_init_register_offset()
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); in ih_v6_1_init_register_offset()
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v6_1_init_register_offset()
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v6_1_init_register_offset()
59 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR); in ih_v6_1_init_register_offset()
60 ih_regs in ih_v6_1_init_register_offset()
131 struct amdgpu_ih_regs *ih_regs; ih_v6_1_toggle_ring_interrupts() local
240 struct amdgpu_ih_regs *ih_regs; ih_v6_1_enable_ring() local
395 struct amdgpu_ih_regs *ih_regs; ih_v6_1_get_wptr() local
444 struct amdgpu_ih_regs *ih_regs; ih_v6_1_irq_rearm() local
469 struct amdgpu_ih_regs *ih_regs; ih_v6_1_set_rptr() local
[all...] |
| H A D | amdgpu_ih.h | 70 struct amdgpu_ih_regs ih_regs; member
|