| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| H A D | rv770_dpm.h | 181 u32 engine_clock,
184 u32 engine_clock, u32 memory_clock,
202 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
205 u32 engine_clock, u32 memory_clock,
227 u32 engine_clock);
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| H A D | rv740_dpm.c | 120 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, in rv740_populate_sclk_value() argument
137 engine_clock, false, ÷rs); in rv740_populate_sclk_value()
143 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
160 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
176 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value()
187 u32 engine_clock, u32 memory_clock, in rv740_populate_mclk_value()
186 rv740_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk) rv740_populate_mclk_value() argument
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| H A D | rv730_dpm.c | 40 u32 engine_clock, in rv730_populate_sclk_value()
57 engine_clock, false, ÷rs); in rv730_populate_sclk_value()
69 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()
92 u32 vco_freq = engine_clock * post_divider; in rv730_populate_sclk_value()
108 sclk->sclk_value = cpu_to_be32(engine_clock); in rv730_populate_sclk_value()
119 u32 engine_clock, u32 memory_clock, in rv730_populate_mclk_value()
39 rv730_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, RV770_SMC_SCLK_VALUE *sclk) rv730_populate_sclk_value() argument
118 rv730_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, LPRV7XX_SMC_MCLK_VALUE mclk) rv730_populate_mclk_value() argument
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| H A D | cypress_dpm.h | 125 u32 engine_clock, u32 memory_clock);
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| H A D | rv770_dpm.c | 386 u32 engine_clock, u32 memory_clock, in rv770_populate_mclk_value()
484 u32 engine_clock, in rv770_populate_sclk_value()
506 engine_clock, false, ÷rs); in rv770_populate_sclk_value()
517 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()
539 u32 vco_freq = engine_clock * post_divider; in rv770_populate_sclk_value()
555 sclk->sclk_value = cpu_to_be32(engine_clock); in rv770_populate_sclk_value()
722 u32 engine_clock) in rv770_calculate_memory_refresh_rate()
733 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in rv770_calculate_memory_refresh_rate()
385 rv770_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk) rv770_populate_mclk_value() argument
483 rv770_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, RV770_SMC_SCLK_VALUE *sclk) rv770_populate_sclk_value() argument
721 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev, u32 engine_clock) rv770_calculate_memory_refresh_rate() argument
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| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| H A D | rv770_dpm.h | 181 u32 engine_clock,
184 u32 engine_clock, u32 memory_clock,
202 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
205 u32 engine_clock, u32 memory_clock,
227 u32 engine_clock);
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| H A D | rv740_dpm.c | 119 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, in rv740_populate_sclk_value() argument
136 engine_clock, false, ÷rs); in rv740_populate_sclk_value()
142 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
159 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
175 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value()
186 u32 engine_clock, u32 memory_clock, in rv740_populate_mclk_value()
185 rv740_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk) rv740_populate_mclk_value() argument
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| H A D | rv730_dpm.c | 38 u32 engine_clock, in rv730_populate_sclk_value()
55 engine_clock, false, ÷rs); in rv730_populate_sclk_value()
67 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()
90 u32 vco_freq = engine_clock * post_divider; in rv730_populate_sclk_value()
106 sclk->sclk_value = cpu_to_be32(engine_clock); in rv730_populate_sclk_value()
117 u32 engine_clock, u32 memory_clock, in rv730_populate_mclk_value()
37 rv730_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, RV770_SMC_SCLK_VALUE *sclk) rv730_populate_sclk_value() argument
116 rv730_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, LPRV7XX_SMC_MCLK_VALUE mclk) rv730_populate_mclk_value() argument
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| H A D | cypress_dpm.h | 125 u32 engine_clock, u32 memory_clock);
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| H A D | rv770_dpm.c | 388 u32 engine_clock, u32 memory_clock, in rv770_populate_mclk_value()
486 u32 engine_clock, in rv770_populate_sclk_value()
508 engine_clock, false, ÷rs); in rv770_populate_sclk_value()
519 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()
541 u32 vco_freq = engine_clock * post_divider; in rv770_populate_sclk_value()
557 sclk->sclk_value = cpu_to_be32(engine_clock); in rv770_populate_sclk_value()
724 u32 engine_clock) in rv770_calculate_memory_refresh_rate()
735 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in rv770_calculate_memory_refresh_rate()
387 rv770_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk) rv770_populate_mclk_value() argument
485 rv770_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, RV770_SMC_SCLK_VALUE *sclk) rv770_populate_sclk_value() argument
723 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev, u32 engine_clock) rv770_calculate_memory_refresh_rate() argument
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu7_hwmgr.c | 3017 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk) in smu7_apply_state_adjust_rules()
3018 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk; in smu7_apply_state_adjust_rules()
3062 sclk = smu7_ps->performance_levels[0].engine_clock; in smu7_apply_state_adjust_rules()
3077 smu7_ps->performance_levels[0].engine_clock = sclk; in smu7_apply_state_adjust_rules()
3080 smu7_ps->performance_levels[1].engine_clock = in smu7_apply_state_adjust_rules()
3081 (smu7_ps->performance_levels[1].engine_clock >= in smu7_apply_state_adjust_rules()
3082 smu7_ps->performance_levels[0].engine_clock) ? in smu7_apply_state_adjust_rules()
3083 smu7_ps->performance_levels[1].engine_clock : in smu7_apply_state_adjust_rules()
3084 smu7_ps->performance_levels[0].engine_clock; in smu7_apply_state_adjust_rules()
3102 smu7_ps->performance_levels[i].engine_clock in smu7_apply_state_adjust_rules()
3424 uint32_t engine_clock, memory_clock; smu7_get_pp_table_entry_callback_func_v0() local
[all...] |
| H A D | ppatomctrl.h | 286 extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);
288 extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
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| H A D | smu7_hwmgr.h | 56 uint32_t engine_clock; member
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| H A D | smu10_hwmgr.h | 76 uint32_t engine_clock; member
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| H A D | smu10_hwmgr.c | 813 smu10_ps->levels[index].engine_clock = 0; in smu10_dpm_get_pp_table_entry_callback()
1041 clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index)); in smu10_get_current_shallow_sleep_clocks()
1042 clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index)); in smu10_get_current_shallow_sleep_clocks()
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| H A D | ppatomctrl.c | 174 uint32_t engine_clock, in atomctrl_set_engine_dram_timings_rv770()
183 cpu_to_le32((engine_clock & SET_CLOCK_FREQ_MASK) | in atomctrl_set_engine_dram_timings_rv770()
1290 const uint32_t engine_clock, in atomctrl_get_engine_clock_spread_spectrum()
1294 ASIC_INTERNAL_ENGINE_SS, engine_clock, ssInfo); in atomctrl_get_engine_clock_spread_spectrum()
172 atomctrl_set_engine_dram_timings_rv770( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock) atomctrl_set_engine_dram_timings_rv770() argument
1288 atomctrl_get_engine_clock_spread_spectrum( struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo) atomctrl_get_engine_clock_spread_spectrum() argument
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | ppatomctrl.h | 300 extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);
303 extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
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| H A D | smu7_hwmgr.c | 3350 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk) in smu7_apply_state_adjust_rules()
3351 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk; in smu7_apply_state_adjust_rules()
3401 sclk = smu7_ps->performance_levels[0].engine_clock; in smu7_apply_state_adjust_rules()
3418 smu7_ps->performance_levels[0].engine_clock = sclk; in smu7_apply_state_adjust_rules()
3421 smu7_ps->performance_levels[1].engine_clock = in smu7_apply_state_adjust_rules()
3422 (smu7_ps->performance_levels[1].engine_clock >= in smu7_apply_state_adjust_rules()
3423 smu7_ps->performance_levels[0].engine_clock) ? in smu7_apply_state_adjust_rules()
3424 smu7_ps->performance_levels[1].engine_clock : in smu7_apply_state_adjust_rules()
3425 smu7_ps->performance_levels[0].engine_clock; in smu7_apply_state_adjust_rules()
3476 smu7_ps->performance_levels[i].engine_clock in smu7_apply_state_adjust_rules()
3798 uint32_t engine_clock, memory_clock; smu7_get_pp_table_entry_callback_func_v0() local
[all...] |
| H A D | smu10_hwmgr.h | 76 uint32_t engine_clock; member
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| H A D | smu7_hwmgr.h | 56 uint32_t engine_clock; member
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| H A D | smu10_hwmgr.c | 897 smu10_ps->levels[index].engine_clock = 0; in smu10_dpm_get_pp_table_entry_callback()
1137 clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index)); in smu10_get_current_shallow_sleep_clocks()
1138 clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index)); in smu10_get_current_shallow_sleep_clocks()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | iceland_smumgr.c | 796 uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk) in iceland_calculate_sclk_params()
811 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); in iceland_calculate_sclk_params()
842 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in iceland_calculate_sclk_params()
863 sclk->SclkFrequency = engine_clock; in iceland_calculate_sclk_params()
892 uint32_t engine_clock, in iceland_populate_single_graphic_level()
898 result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level); in iceland_populate_single_graphic_level()
902 hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, in iceland_populate_single_graphic_level()
908 graphic_level->SclkFrequency = engine_clock; in iceland_populate_single_graphic_level()
914 engine_clock, in iceland_populate_single_graphic_level()
937 smu7_get_sleep_divider_id_from_clock(engine_clock, in iceland_populate_single_graphic_level()
795 iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr, uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk) iceland_calculate_sclk_params() argument
891 iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *graphic_level) iceland_populate_single_graphic_level() argument
1582 iceland_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs ) iceland_populate_memory_timing_parameters() argument
[all...] |
| H A D | tonga_smumgr.c | 539 uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk) in tonga_calculate_sclk_params()
554 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); in tonga_calculate_sclk_params()
585 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in tonga_calculate_sclk_params()
606 sclk->SclkFrequency = engine_clock; in tonga_calculate_sclk_params()
617 uint32_t engine_clock, in tonga_populate_single_graphic_level()
627 result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level); in tonga_populate_single_graphic_level()
636 vdd_dep_table, engine_clock, in tonga_populate_single_graphic_level()
643 graphic_level->SclkFrequency = engine_clock; in tonga_populate_single_graphic_level()
664 smu7_get_sleep_divider_id_from_clock(engine_clock, in tonga_populate_single_graphic_level()
1459 uint32_t engine_clock, in tonga_populate_memory_timing_parameters()
538 tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr, uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk) tonga_calculate_sclk_params() argument
616 tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *graphic_level) tonga_populate_single_graphic_level() argument
1457 tonga_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs ) tonga_populate_memory_timing_parameters() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | iceland_smumgr.c | 796 uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk) in iceland_calculate_sclk_params()
811 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); in iceland_calculate_sclk_params()
842 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in iceland_calculate_sclk_params()
863 sclk->SclkFrequency = engine_clock; in iceland_calculate_sclk_params()
892 uint32_t engine_clock, in iceland_populate_single_graphic_level()
898 result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level); in iceland_populate_single_graphic_level()
902 hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, in iceland_populate_single_graphic_level()
908 graphic_level->SclkFrequency = engine_clock; in iceland_populate_single_graphic_level()
914 engine_clock, in iceland_populate_single_graphic_level()
937 smu7_get_sleep_divider_id_from_clock(engine_clock, in iceland_populate_single_graphic_level()
795 iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr, uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk) iceland_calculate_sclk_params() argument
891 iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *graphic_level) iceland_populate_single_graphic_level() argument
1582 iceland_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs ) iceland_populate_memory_timing_parameters() argument
[all...] |
| H A D | tonga_smumgr.c | 539 uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk) in tonga_calculate_sclk_params()
554 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); in tonga_calculate_sclk_params()
585 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in tonga_calculate_sclk_params()
606 sclk->SclkFrequency = engine_clock; in tonga_calculate_sclk_params()
617 uint32_t engine_clock, in tonga_populate_single_graphic_level()
627 result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level); in tonga_populate_single_graphic_level()
636 vdd_dep_table, engine_clock, in tonga_populate_single_graphic_level()
643 graphic_level->SclkFrequency = engine_clock; in tonga_populate_single_graphic_level()
664 smu7_get_sleep_divider_id_from_clock(engine_clock, in tonga_populate_single_graphic_level()
1459 uint32_t engine_clock, in tonga_populate_memory_timing_parameters()
538 tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr, uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk) tonga_calculate_sclk_params() argument
616 tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *graphic_level) tonga_populate_single_graphic_level() argument
1457 tonga_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs ) tonga_populate_memory_timing_parameters() argument
[all...] |