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Searched refs:WREG32_PCIE (Results 1 - 25 of 46) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v6_1.c189 WREG32_PCIE(smnCPM_CONTROL, data); in nbio_v6_1_update_medium_grain_clock_gating()
209 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v6_1_update_medium_grain_light_sleep()
272 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); in nbio_v6_1_init_registers()
278 WREG32_PCIE(smnPCIE_CI_CNTL, data); in nbio_v6_1_init_registers()
290 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB); in nbio_v6_1_program_ltr()
295 WREG32_PCIE(smnRCC_BIF_STRAP2, data); in nbio_v6_1_program_ltr()
300 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); in nbio_v6_1_program_ltr()
305 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); in nbio_v6_1_program_ltr()
319 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v6_1_program_aspm()
324 WREG32_PCIE(smnPCIE_LC_CNTL in nbio_v6_1_program_aspm()
[all...]
H A Dnbio_v7_4.c272 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v7_4_update_medium_grain_light_sleep()
619 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO_ALDE, global_sts); in nbio_v7_4_query_ras_error_count()
621 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts); in nbio_v7_4_query_ras_error_count()
627 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE, parity_sts); in nbio_v7_4_query_ras_error_count()
629 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2, parity_sts); in nbio_v7_4_query_ras_error_count()
635 WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts); in nbio_v7_4_query_ras_error_count()
639 WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi); in nbio_v7_4_query_ras_error_count()
681 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB); in nbio_v7_4_program_ltr()
686 WREG32_PCIE(smnRCC_BIF_STRAP2, data); in nbio_v7_4_program_ltr()
691 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNT in nbio_v7_4_program_ltr()
[all...]
H A Dnbio_v2_3.c255 WREG32_PCIE(smnCPM_CONTROL, data); in nbio_v2_3_update_medium_grain_clock_gating()
278 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v2_3_update_medium_grain_light_sleep()
341 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); in nbio_v2_3_init_registers()
381 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v2_3_enable_aspm()
389 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB); in nbio_v2_3_program_ltr()
399 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); in nbio_v2_3_program_ltr()
404 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); in nbio_v2_3_program_ltr()
418 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v2_3_program_aspm()
423 WREG32_PCIE(smnPCIE_LC_CNTL7, data); in nbio_v2_3_program_aspm()
428 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCL in nbio_v2_3_program_aspm()
[all...]
H A Dumc_v6_1.c56 WREG32_PCIE(rsmu_umc_addr * 4, rsmu_umc_val); in umc_v6_1_enable_umc_index_mode()
71 WREG32_PCIE(rsmu_umc_addr * 4, rsmu_umc_val); in umc_v6_1_disable_umc_index_mode()
124 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
128 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
137 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
141 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
200 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_query_correctable_error_count()
210 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_query_correctable_error_count()
418 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_err_cnt_init_per_channel()
420 WREG32_PCIE((ecc_err_cnt_add in umc_v6_1_err_cnt_init_per_channel()
[all...]
H A Dumc_v8_7.c197 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
201 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
210 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
214 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
255 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_query_correctable_error_count()
265 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_query_correctable_error_count()
408 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_err_cnt_init_per_channel()
410 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_7_CE_CNT_INIT); in umc_v8_7_err_cnt_init_per_channel()
415 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_err_cnt_init_per_channel()
416 WREG32_PCIE((ecc_err_cnt_add in umc_v8_7_err_cnt_init_per_channel()
[all...]
H A Dcik.c1596 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, tmp); in cik_pcie_gen3_enable()
1622 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1626 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1666 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1675 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
1690 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
1721 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); in cik_program_aspm()
1726 WREG32_PCIE(ixPCIE_LC_CNTL3, data); in cik_program_aspm()
1731 WREG32_PCIE(ixPCIE_P_CNTL, data); in cik_program_aspm()
1744 WREG32_PCIE(ixPCIE_LC_CNT in cik_program_aspm()
[all...]
H A Dumc_v6_7.c284 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_7_query_correctable_error_count()
294 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_7_query_correctable_error_count()
383 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
387 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
396 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
400 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
H A Dvi.c1118 WREG32_PCIE(ixPCIE_LC_CNTL, data); in vi_enable_aspm()
1139 WREG32_PCIE(ixPCIE_LC_CNTL, data); in vi_program_aspm()
1146 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); in vi_program_aspm()
1151 WREG32_PCIE(ixPCIE_LC_CNTL3, data); in vi_program_aspm()
1156 WREG32_PCIE(ixPCIE_P_CNTL, data); in vi_program_aspm()
1176 WREG32_PCIE(ixPCIE_LC_CNTL6, data); in vi_program_aspm()
1181 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data); in vi_program_aspm()
1224 WREG32_PCIE(ixCPM_CONTROL, data); in vi_program_aspm()
1230 WREG32_PCIE(ixPCIE_CONFIG_CNTL, data); in vi_program_aspm()
1240 WREG32_PCIE(ixPCIE_LC_CNTL in vi_program_aspm()
[all...]
H A Dnbio_v7_9.c503 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctrrx); in nbio_v7_9_get_pcie_usage()
504 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK7, perfctrtx); in nbio_v7_9_get_pcie_usage()
511 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000006); in nbio_v7_9_get_pcie_usage()
517 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000001); in nbio_v7_9_get_pcie_usage()
526 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000006); in nbio_v7_9_get_pcie_usage()
H A Dnbio_v7_0.c162 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); in nbio_v7_0_update_medium_grain_clock_gating()
204 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v7_0_update_medium_grain_light_sleep()
H A Dumc_v8_10.c91 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_10_clear_error_count_per_channel()
313 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_10_err_cnt_init_per_channel()
315 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_10_CE_CNT_INIT); in umc_v8_10_err_cnt_init_per_channel()
H A Dsoc15.c747 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); in soc15_get_pcie_usage()
753 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); in soc15_get_pcie_usage()
762 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); in soc15_get_pcie_usage()
796 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); in vega20_get_pcie_usage()
802 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); in vega20_get_pcie_usage()
811 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); in vega20_get_pcie_usage()
H A Damdgpu_xgmi.c905 WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF); in pcs_clear_status()
906 WREG32_PCIE(pcs_status_reg, 0); in pcs_clear_status()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dumc_v8_7.c66 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
70 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
79 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
83 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
124 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_query_correctable_error_count()
134 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_query_correctable_error_count()
300 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_err_cnt_init_per_channel()
302 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_7_CE_CNT_INIT); in umc_v8_7_err_cnt_init_per_channel()
307 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_err_cnt_init_per_channel()
308 WREG32_PCIE((ecc_err_cnt_add in umc_v8_7_err_cnt_init_per_channel()
[all...]
H A Dumc_v6_1.c55 WREG32_PCIE(rsmu_umc_addr * 4, rsmu_umc_val); in umc_v6_1_enable_umc_index_mode()
70 WREG32_PCIE(rsmu_umc_addr * 4, rsmu_umc_val); in umc_v6_1_disable_umc_index_mode()
123 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
127 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
136 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
140 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
199 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_query_correctable_error_count()
209 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_query_correctable_error_count()
433 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_err_cnt_init_per_channel()
435 WREG32_PCIE((ecc_err_cnt_add in umc_v6_1_err_cnt_init_per_channel()
[all...]
H A Dnbio_v6_1.c170 WREG32_PCIE(smnCPM_CONTROL, data); in nbio_v6_1_update_medium_grain_clock_gating()
190 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v6_1_update_medium_grain_light_sleep()
253 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); in nbio_v6_1_init_registers()
259 WREG32_PCIE(smnPCIE_CI_CNTL, data); in nbio_v6_1_init_registers()
H A Dcik.c1531 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, tmp); in cik_pcie_gen3_enable()
1557 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1561 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1601 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1610 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
1625 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
1656 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); in cik_program_aspm()
1661 WREG32_PCIE(ixPCIE_LC_CNTL3, data); in cik_program_aspm()
1666 WREG32_PCIE(ixPCIE_P_CNTL, data); in cik_program_aspm()
1679 WREG32_PCIE(ixPCIE_LC_CNT in cik_program_aspm()
[all...]
H A Dnbio_v7_4.c219 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v7_4_update_medium_grain_light_sleep()
511 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts); in nbio_v7_4_query_ras_error_count()
515 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2, in nbio_v7_4_query_ras_error_count()
521 WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts); in nbio_v7_4_query_ras_error_count()
525 WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi); in nbio_v7_4_query_ras_error_count()
H A Dnbio_v2_3.c229 WREG32_PCIE(smnCPM_CONTROL, data); in nbio_v2_3_update_medium_grain_clock_gating()
249 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v2_3_update_medium_grain_light_sleep()
312 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); in nbio_v2_3_init_registers()
H A Dnbio_v7_0.c171 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); in nbio_v7_0_update_medium_grain_clock_gating()
213 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v7_0_update_medium_grain_light_sleep()
H A Dsoc15.c889 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); in soc15_get_pcie_usage()
895 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); in soc15_get_pcie_usage()
904 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); in soc15_get_pcie_usage()
938 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); in vega20_get_pcie_usage()
944 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); in vega20_get_pcie_usage()
953 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); in vega20_get_pcie_usage()
H A Dvi.c1022 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr); in vi_get_pcie_usage()
1028 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005); in vi_get_pcie_usage()
1037 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002); in vi_get_pcie_usage()
1432 WREG32_PCIE(ixPCIE_CNTL2, data); in vi_update_bif_medium_grain_light_sleep()
H A Damdgpu_xgmi.c687 WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF); in pcs_clear_status()
688 WREG32_PCIE(pcs_status_reg, 0); in pcs_clear_status()
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dr300.c96 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); in rv370_pcie_gart_tlb_flush()
98 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_tlb_flush()
168 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable()
169 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); in rv370_pcie_gart_enable()
171 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); in rv370_pcie_gart_enable()
172 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); in rv370_pcie_gart_enable()
173 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); in rv370_pcie_gart_enable()
175 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); in rv370_pcie_gart_enable()
177 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); in rv370_pcie_gart_enable()
178 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_H in rv370_pcie_gart_enable()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dr300.c94 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); in rv370_pcie_gart_tlb_flush()
96 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_tlb_flush()
165 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable()
166 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); in rv370_pcie_gart_enable()
168 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); in rv370_pcie_gart_enable()
169 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); in rv370_pcie_gart_enable()
170 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); in rv370_pcie_gart_enable()
172 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); in rv370_pcie_gart_enable()
174 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); in rv370_pcie_gart_enable()
175 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_H in rv370_pcie_gart_enable()
[all...]

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