Lines Matching refs:WREG32_PCIE
96 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
98 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
168 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
169 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
171 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
172 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
173 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
175 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
177 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
178 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
180 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
184 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
197 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
198 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
199 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
200 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
203 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
550 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
551 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |