Lines Matching refs:WREG32_PCIE
94 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
96 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
165 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
166 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
168 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
169 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
170 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
172 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
174 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
175 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
177 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
181 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
194 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
195 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
196 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
197 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
200 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
547 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
548 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |