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Searched refs:VC4_SET_FIELD (Results 1 - 25 of 26) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/vc4/
H A Dvc4_hdmi_phy.c374 VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT)); in vc5_hdmi_phy_init()
379 VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT)); in vc5_hdmi_phy_init()
382 VC4_SET_FIELD(phy_get_rm_offset(vco_freq), in vc5_hdmi_phy_init()
387 VC4_SET_FIELD(vco_div, VC4_HDMI_TX_PHY_CLK_DIV_VCO)); in vc5_hdmi_phy_init()
390 VC4_SET_FIELD(0xe147, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD) | in vc5_hdmi_phy_init()
391 VC4_SET_FIELD(0xe14, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD)); in vc5_hdmi_phy_init()
397 VC4_SET_FIELD(vco_sel, VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_SEL)); in vc5_hdmi_phy_init()
402 VC4_SET_FIELD(3, VC4_HDMI_TX_PHY_PLL_CTL_1_POST_RST_SEL) | in vc5_hdmi_phy_init()
403 VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_DELAY) | in vc5_hdmi_phy_init()
404 VC4_SET_FIELD( in vc5_hdmi_phy_init()
[all...]
H A Dvc4_plane.c427 VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) | in vc4_write_tpz()
428 VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE)); in vc4_write_tpz()
430 VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP)); in vc4_write_tpz()
439 VC4_SET_FIELD(scale, SCALER_PPF_SCALE) | in vc4_write_ppf()
440 VC4_SET_FIELD(0, SCALER_PPF_IPHASE)); in vc4_write_ppf()
679 pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH); in vc4_plane_mode_set()
742 pitch0 |= (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) | in vc4_plane_mode_set()
743 VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) | in vc4_plane_mode_set()
744 VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) | in vc4_plane_mode_set()
745 VC4_SET_FIELD(tiles_ in vc4_plane_mode_set()
[all...]
H A Dvc4_dsi.c929 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | in vc4_dsi_encoder_enable()
930 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ)); in vc4_dsi_encoder_enable()
944 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) | in vc4_dsi_encoder_enable()
945 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) | in vc4_dsi_encoder_enable()
946 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE)); in vc4_dsi_encoder_enable()
948 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | in vc4_dsi_encoder_enable()
949 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) | in vc4_dsi_encoder_enable()
950 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) | in vc4_dsi_encoder_enable()
951 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) | in vc4_dsi_encoder_enable()
952 VC4_SET_FIELD( in vc4_dsi_encoder_enable()
[all...]
H A Dvc4_kms.c159 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]), in vc4_ctm_commit()
161 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]), in vc4_ctm_commit()
163 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]), in vc4_ctm_commit()
166 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]), in vc4_ctm_commit()
168 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]), in vc4_ctm_commit()
170 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]), in vc4_ctm_commit()
173 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]), in vc4_ctm_commit()
175 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]), in vc4_ctm_commit()
177 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]), in vc4_ctm_commit()
182 VC4_SET_FIELD(ctm_stat in vc4_ctm_commit()
[all...]
H A Dvc4_crtc.c268 ret |= VC4_SET_FIELD((level >> 6), in vc4_crtc_get_fifo_full_level_bits()
271 return ret | VC4_SET_FIELD(level & 0x3f, in vc4_crtc_get_fifo_full_level_bits()
337 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc, in vc4_crtc_config_pv()
339 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc, in vc4_crtc_config_pv()
343 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc, in vc4_crtc_config_pv()
345 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc, in vc4_crtc_config_pv()
349 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + in vc4_crtc_config_pv()
352 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, in vc4_crtc_config_pv()
355 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, in vc4_crtc_config_pv()
357 VC4_SET_FIELD(mod in vc4_crtc_config_pv()
[all...]
H A Dvc4_hdmi.c442 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, in vc4_hdmi_csc_setup()
458 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, in vc4_hdmi_csc_setup()
519 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, in vc4_hdmi_set_timings()
521 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, in vc4_hdmi_set_timings()
523 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); in vc4_hdmi_set_timings()
524 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | in vc4_hdmi_set_timings()
525 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + in vc4_hdmi_set_timings()
528 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | in vc4_hdmi_set_timings()
529 VC4_SET_FIELD(mode->crtc_vtotal - in vc4_hdmi_set_timings()
536 VC4_SET_FIELD(mod in vc4_hdmi_set_timings()
[all...]
H A Dvc4_dpi.c157 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
161 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
163 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, in vc4_dpi_encoder_enable()
167 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2, in vc4_dpi_encoder_enable()
171 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, in vc4_dpi_encoder_enable()
175 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_1, in vc4_dpi_encoder_enable()
192 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, DPI_FORMAT); in vc4_dpi_encoder_enable()
H A Dvc4_hvs.c274 dispctrl |= VC4_SET_FIELD(mode->hdisplay, in vc4_hvs_init_channel()
276 VC4_SET_FIELD(mode->vdisplay, in vc4_hvs_init_channel()
280 dispctrl |= VC4_SET_FIELD(mode->hdisplay, in vc4_hvs_init_channel()
282 VC4_SET_FIELD(mode->vdisplay, in vc4_hvs_init_channel()
642 reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX)); in vc4_hvs_bind()
647 reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX)); in vc4_hvs_bind()
652 reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX)); in vc4_hvs_bind()
657 reg | VC4_SET_FIELD(3, SCALER_DISPDITHER_DSP5_MUX)); in vc4_hvs_bind()
687 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0); in vc4_hvs_bind()
688 dispctrl |= VC4_SET_FIELD( in vc4_hvs_bind()
[all...]
H A Dvc4_txp.c299 VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) | in vc4_txp_connector_atomic_commit()
300 VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT); in vc4_txp_connector_atomic_commit()
315 VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) | in vc4_txp_connector_atomic_commit()
316 VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT)); in vc4_txp_connector_atomic_commit()
H A Dvc4_gem.c441 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | in vc4_flush_caches()
442 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) | in vc4_flush_caches()
443 VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) | in vc4_flush_caches()
444 VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC)); in vc4_flush_caches()
456 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | in vc4_flush_texture_caches()
457 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC)); in vc4_flush_texture_caches()
H A Dvc4_validate.c409 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32, in validate_tile_binning_config()
411 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128, in validate_tile_binning_config()
H A Dvc4_render_cl.c84 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE, in vc4_store_before_load()
H A Dvc4_regs.h14 #define VC4_SET_FIELD(value, field) \ macro
/kernel/linux/linux-6.6/drivers/gpu/drm/vc4/
H A Dvc4_hdmi_phy.c399 VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT)); in vc5_hdmi_phy_init()
404 VC4_SET_FIELD(0, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT)); in vc5_hdmi_phy_init()
407 VC4_SET_FIELD(phy_get_rm_offset(vco_freq), in vc5_hdmi_phy_init()
412 VC4_SET_FIELD(vco_div, VC4_HDMI_TX_PHY_CLK_DIV_VCO)); in vc5_hdmi_phy_init()
415 VC4_SET_FIELD(0xe147, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD) | in vc5_hdmi_phy_init()
416 VC4_SET_FIELD(0xe14, VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD)); in vc5_hdmi_phy_init()
422 VC4_SET_FIELD(vco_sel, VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_SEL)); in vc5_hdmi_phy_init()
427 VC4_SET_FIELD(3, VC4_HDMI_TX_PHY_PLL_CTL_1_POST_RST_SEL) | in vc5_hdmi_phy_init()
428 VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_DELAY) | in vc5_hdmi_phy_init()
429 VC4_SET_FIELD( in vc5_hdmi_phy_init()
[all...]
H A Dvc4_dpi.c160 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, DPI_FORMAT); in vc4_dpi_encoder_enable()
170 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
174 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
176 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, in vc4_dpi_encoder_enable()
180 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER); in vc4_dpi_encoder_enable()
183 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2, in vc4_dpi_encoder_enable()
187 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER); in vc4_dpi_encoder_enable()
190 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, in vc4_dpi_encoder_enable()
194 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_1, in vc4_dpi_encoder_enable()
198 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_ in vc4_dpi_encoder_enable()
[all...]
H A Dvc4_dsi.c943 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | in vc4_dsi_bridge_pre_enable()
944 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ)); in vc4_dsi_bridge_pre_enable()
958 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) | in vc4_dsi_bridge_pre_enable()
959 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) | in vc4_dsi_bridge_pre_enable()
960 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE)); in vc4_dsi_bridge_pre_enable()
962 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | in vc4_dsi_bridge_pre_enable()
963 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) | in vc4_dsi_bridge_pre_enable()
964 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) | in vc4_dsi_bridge_pre_enable()
965 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) | in vc4_dsi_bridge_pre_enable()
966 VC4_SET_FIELD( in vc4_dsi_bridge_pre_enable()
[all...]
H A Dvc4_plane.c534 VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) | in vc4_write_tpz()
535 VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE)); in vc4_write_tpz()
537 VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP)); in vc4_write_tpz()
546 VC4_SET_FIELD(scale, SCALER_PPF_SCALE) | in vc4_write_ppf()
547 VC4_SET_FIELD(0, SCALER_PPF_IPHASE)); in vc4_write_ppf()
772 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_FIXED, in vc4_hvs4_get_alpha_blend_mode()
777 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_FIXED, in vc4_hvs4_get_alpha_blend_mode()
781 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_PIPELINE, in vc4_hvs4_get_alpha_blend_mode()
785 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_PIPELINE, in vc4_hvs4_get_alpha_blend_mode()
793 return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_FIXE in vc4_hvs5_get_alpha_blend_mode()
[all...]
H A Dvc4_kms.c143 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]), in vc4_ctm_commit()
145 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]), in vc4_ctm_commit()
147 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]), in vc4_ctm_commit()
150 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]), in vc4_ctm_commit()
152 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]), in vc4_ctm_commit()
154 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]), in vc4_ctm_commit()
157 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]), in vc4_ctm_commit()
159 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]), in vc4_ctm_commit()
161 VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]), in vc4_ctm_commit()
166 VC4_SET_FIELD(ctm_stat in vc4_ctm_commit()
[all...]
H A Dvc4_crtc.c279 ret |= VC4_SET_FIELD((level >> 6), in vc4_crtc_get_fifo_full_level_bits()
282 return ret | VC4_SET_FIELD(level & 0x3f, in vc4_crtc_get_fifo_full_level_bits()
363 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc, in vc4_crtc_config_pv()
365 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc, in vc4_crtc_config_pv()
369 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc, in vc4_crtc_config_pv()
371 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc, in vc4_crtc_config_pv()
395 VC4_SET_FIELD(vert_bp_even, PV_VERTA_VBP) | in vc4_crtc_config_pv()
396 VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC)); in vc4_crtc_config_pv()
398 VC4_SET_FIELD(vert_fp_even, PV_VERTB_VFP) | in vc4_crtc_config_pv()
399 VC4_SET_FIELD(mod in vc4_crtc_config_pv()
[all...]
H A Dvc4_hdmi.c1174 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, in vc4_hdmi_csc_setup()
1190 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, in vc4_hdmi_csc_setup()
1408 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, in vc5_hdmi_csc_setup()
1427 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, in vc5_hdmi_csc_setup()
1432 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, in vc5_hdmi_csc_setup()
1435 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, in vc5_hdmi_csc_setup()
1470 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, in vc4_hdmi_set_timings()
1472 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, in vc4_hdmi_set_timings()
1474 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); in vc4_hdmi_set_timings()
1475 u32 vertb = (VC4_SET_FIELD( in vc4_hdmi_set_timings()
[all...]
H A Dvc4_hvs.c376 dispctrl |= VC4_SET_FIELD(mode->hdisplay, in vc4_hvs_init_channel()
378 VC4_SET_FIELD(mode->vdisplay, in vc4_hvs_init_channel()
383 dispctrl |= VC4_SET_FIELD(mode->hdisplay, in vc4_hvs_init_channel()
385 VC4_SET_FIELD(mode->vdisplay, in vc4_hvs_init_channel()
901 reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX)); in vc4_hvs_bind()
906 reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX)); in vc4_hvs_bind()
911 reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX)); in vc4_hvs_bind()
916 reg | VC4_SET_FIELD(3, SCALER_DISPDITHER_DSP5_MUX)); in vc4_hvs_bind()
961 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0); in vc4_hvs_bind()
962 dispctrl |= VC4_SET_FIELD( in vc4_hvs_bind()
[all...]
H A Dvc4_txp.c311 VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) | in vc4_txp_connector_atomic_commit()
312 VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT); in vc4_txp_connector_atomic_commit()
330 VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) | in vc4_txp_connector_atomic_commit()
331 VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT)); in vc4_txp_connector_atomic_commit()
H A Dvc4_gem.c447 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | in vc4_flush_caches()
448 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) | in vc4_flush_caches()
449 VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) | in vc4_flush_caches()
450 VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC)); in vc4_flush_caches()
462 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | in vc4_flush_texture_caches()
463 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC)); in vc4_flush_texture_caches()
H A Dvc4_validate.c417 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32, in validate_tile_binning_config()
419 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128, in validate_tile_binning_config()
H A Dvc4_render_cl.c84 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE, in vc4_store_before_load()

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