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Searched refs:VC4_MASK (Results 1 - 12 of 12) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/vc4/
H A Dvc4_regs.h12 #define VC4_MASK(high, low) ((u32)GENMASK(high, low)) macro
31 # define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28)
33 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)
35 # define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12)
37 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
39 # define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4)
41 # define V3D_IDENT1_REV_MASK VC4_MASK(3, 0)
52 # define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24)
54 # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16)
56 # define V3D_SLCACTL_UCC_MASK VC4_MASK(1
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H A Dvc4_packet.h27 #include "vc4_regs.h" /* for VC4_MASK, VC4_GET_FIELD, VC4_SET_FIELD */
183 #define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK VC4_MASK(9, 8)
195 #define VC4_STORE_TILE_BUFFER_MODE_MASK VC4_MASK(7, 6)
202 #define VC4_LOADSTORE_TILE_BUFFER_TILING_MASK VC4_MASK(5, 4)
205 #define VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK VC4_MASK(2, 0)
258 #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK VC4_MASK(6, 5)
265 #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_MASK VC4_MASK(4, 3)
285 #define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK VC4_MASK(7, 6)
292 #define VC4_RENDER_CONFIG_FORMAT_MASK VC4_MASK(3, 2)
329 #define VC4_TEX_P0_OFFSET_MASK VC4_MASK(3
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H A Dvc4_hdmi_phy.c23 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_PREEMP_MASK VC4_MASK(31, 29)
25 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_MAINDRV_MASK VC4_MASK(28, 24)
27 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_PREEMP_MASK VC4_MASK(23, 21)
29 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_MAINDRV_MASK VC4_MASK(20, 16)
31 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_PREEMP_MASK VC4_MASK(15, 13)
33 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_MAINDRV_MASK VC4_MASK(12, 8)
35 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_PREEMP_MASK VC4_MASK(7, 5)
37 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_MASK VC4_MASK(4, 0)
40 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA2_MASK VC4_MASK(19, 15)
42 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA1_MASK VC4_MASK(1
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H A Dvc4_dsi.c54 # define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24)
56 # define DSI_TXPKT1C_CMD_REPEAT_MASK VC4_MASK(23, 10)
59 # define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8)
72 # define DSI_TXPKT1C_CMD_TX_TIME_MASK VC4_MASK(7, 6)
75 # define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4)
96 # define DSI_TXPKT1H_BC_CMDFIFO_MASK VC4_MASK(31, 24)
98 # define DSI_TXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
100 # define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0)
112 # define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
115 # define DSI_RXPKT1H_SHORT_1_MASK VC4_MASK(2
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H A Dvc4_dpi.c34 # define DPI_ORDER_MASK VC4_MASK(15, 14)
44 # define DPI_FORMAT_MASK VC4_MASK(13, 11)
H A Dvc4_hdmi.c58 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
62 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
65 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
67 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
70 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
72 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
74 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
77 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
/kernel/linux/linux-6.6/drivers/gpu/drm/vc4/
H A Dvc4_regs.h12 #define VC4_MASK(high, low) ((u32)GENMASK(high, low)) macro
31 # define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28)
33 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)
35 # define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12)
37 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
39 # define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4)
41 # define V3D_IDENT1_REV_MASK VC4_MASK(3, 0)
52 # define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24)
54 # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16)
56 # define V3D_SLCACTL_UCC_MASK VC4_MASK(1
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H A Dvc4_packet.h27 #include "vc4_regs.h" /* for VC4_MASK, VC4_GET_FIELD, VC4_SET_FIELD */
183 #define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK VC4_MASK(9, 8)
195 #define VC4_STORE_TILE_BUFFER_MODE_MASK VC4_MASK(7, 6)
202 #define VC4_LOADSTORE_TILE_BUFFER_TILING_MASK VC4_MASK(5, 4)
205 #define VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK VC4_MASK(2, 0)
258 #define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK VC4_MASK(6, 5)
265 #define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_MASK VC4_MASK(4, 3)
285 #define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK VC4_MASK(7, 6)
292 #define VC4_RENDER_CONFIG_FORMAT_MASK VC4_MASK(3, 2)
329 #define VC4_TEX_P0_OFFSET_MASK VC4_MASK(3
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H A Dvc4_hdmi_phy.c23 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_PREEMP_MASK VC4_MASK(31, 29)
25 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_MAINDRV_MASK VC4_MASK(28, 24)
27 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_PREEMP_MASK VC4_MASK(23, 21)
29 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_MAINDRV_MASK VC4_MASK(20, 16)
31 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_PREEMP_MASK VC4_MASK(15, 13)
33 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_MAINDRV_MASK VC4_MASK(12, 8)
35 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_PREEMP_MASK VC4_MASK(7, 5)
37 #define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_MASK VC4_MASK(4, 0)
40 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA2_MASK VC4_MASK(19, 15)
42 #define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA1_MASK VC4_MASK(1
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H A Dvc4_dsi.c54 # define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24)
56 # define DSI_TXPKT1C_CMD_REPEAT_MASK VC4_MASK(23, 10)
59 # define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8)
72 # define DSI_TXPKT1C_CMD_TX_TIME_MASK VC4_MASK(7, 6)
75 # define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4)
96 # define DSI_TXPKT1H_BC_CMDFIFO_MASK VC4_MASK(31, 24)
98 # define DSI_TXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
100 # define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0)
112 # define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
115 # define DSI_RXPKT1H_SHORT_1_MASK VC4_MASK(2
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H A Dvc4_dpi.c36 # define DPI_ORDER_MASK VC4_MASK(15, 14)
46 # define DPI_FORMAT_MASK VC4_MASK(13, 11)
H A Dvc4_hdmi.c61 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
65 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
68 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
70 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
73 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
75 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
77 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
80 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
83 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
85 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(
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