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Searched refs:SR_INT (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/drivers/macintosh/
H A Dvia-cuda.c84 #define SR_INT 0x04 /* Shift register full/empty */ macro
275 out_8(&via[IER], IER_SET|SR_INT); /* enable interrupt from SR */ in find_via_cuda()
360 if (in_8(&via[IFR]) & SR_INT) in sync_egret()
384 out_8(&via[IER], SR_INT); /* disable SR interrupt from VIA */ in cuda_init_via()
399 out_8(&via[IFR], SR_INT); in cuda_init_via()
408 WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (2)"); in cuda_init_via()
410 out_8(&via[IFR], SR_INT); in cuda_init_via()
417 WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (4)"); in cuda_init_via()
419 out_8(&via[IFR], SR_INT); in cuda_init_via()
586 if ((in_8(&via[IFR]) & SR_INT) in cuda_interrupt()
[all...]
H A Dvia-macii.c72 #define SR_INT 0x04 /* Shift register full/empty */ macro
357 * generating shift register interrupts (SR_INT) for us. This means there has
362 * register which eventually raises the SR_INT interrupt. The PB4/PB5 outputs
382 if (via[IFR] & SR_INT) in macii_interrupt()
383 via[IFR] = SR_INT; in macii_interrupt()
H A Dvia-pmu.c119 #define SR_INT 0x04 /* Shift register full/empty */ macro
476 out_8(&via1[IER], IER_SET | SR_INT | CB1_INT); in via_pmu_start()
1601 intr = in_8(&via1[IFR]) & (SR_INT | CB1_INT); in via_pmu_interrupt()
1610 intr = SR_INT; in via_pmu_interrupt()
1627 if (intr & SR_INT) { in via_pmu_interrupt()
1862 out_8(&via1[IER], IER_SET | SR_INT | CB1_INT); in restore_via_state()
/kernel/linux/linux-6.6/drivers/macintosh/
H A Dvia-cuda.c87 #define SR_INT 0x04 /* Shift register full/empty */ macro
272 out_8(&via[IER], IER_SET|SR_INT); /* enable interrupt from SR */ in find_via_cuda()
357 if (in_8(&via[IFR]) & SR_INT) in sync_egret()
381 out_8(&via[IER], SR_INT); /* disable SR interrupt from VIA */ in cuda_init_via()
396 out_8(&via[IFR], SR_INT); in cuda_init_via()
405 WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (2)"); in cuda_init_via()
407 out_8(&via[IFR], SR_INT); in cuda_init_via()
414 WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (4)"); in cuda_init_via()
416 out_8(&via[IFR], SR_INT); in cuda_init_via()
583 if ((in_8(&via[IFR]) & SR_INT) in cuda_interrupt()
[all...]
H A Dvia-macii.c70 #define SR_INT 0x04 /* Shift register full/empty */ macro
355 * generating shift register interrupts (SR_INT) for us. This means there has
360 * register which eventually raises the SR_INT interrupt. The PB4/PB5 outputs
380 if (via[IFR] & SR_INT) in macii_interrupt()
381 via[IFR] = SR_INT; in macii_interrupt()
H A Dvia-pmu.c118 #define SR_INT 0x04 /* Shift register full/empty */ macro
465 out_8(&via1[IER], IER_SET | SR_INT | CB1_INT); in via_pmu_start()
1592 intr = in_8(&via1[IFR]) & (SR_INT | CB1_INT); in via_pmu_interrupt()
1601 intr = SR_INT; in via_pmu_interrupt()
1618 if (intr & SR_INT) { in via_pmu_interrupt()
1854 out_8(&via1[IER], IER_SET | SR_INT | CB1_INT); in restore_via_state()

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