Lines Matching refs:SR_INT
87 #define SR_INT 0x04 /* Shift register full/empty */
272 out_8(&via[IER], IER_SET|SR_INT); /* enable interrupt from SR */
357 if (in_8(&via[IFR]) & SR_INT)
381 out_8(&via[IER], SR_INT); /* disable SR interrupt from VIA */
396 out_8(&via[IFR], SR_INT);
405 WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (2)");
407 out_8(&via[IFR], SR_INT);
414 WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (4)");
416 out_8(&via[IFR], SR_INT);
583 if ((in_8(&via[IFR]) & SR_INT) == 0) {
587 out_8(&via[IFR], SR_INT);