Home
last modified time | relevance | path

Searched refs:SET_REG (Results 1 - 14 of 14) sorted by relevance

/kernel/linux/linux-5.10/sound/pci/hda/
H A Dpatch_si3054.c65 #define SET_REG(codec,reg,val) (snd_hda_codec_write(codec,reg,0,SI3054_VERB_WRITE_NODE,val)) macro
143 SET_REG(codec, SI3054_LINE_RATE, substream->runtime->rate); in si3054_pcm_prepare()
147 SET_REG(codec, SI3054_LINE_LEVEL, val); in si3054_pcm_prepare()
217 SET_REG(codec, SI3054_LINE_RATE, 9600); in si3054_init()
218 SET_REG(codec, SI3054_LINE_LEVEL, SI3054_DTAG_MASK|SI3054_ATAG_MASK); in si3054_init()
219 SET_REG(codec, SI3054_EXTENDED_MID, 0); in si3054_init()
233 SET_REG(codec, SI3054_GPIO_POLARITY, 0xffff); in si3054_init()
234 SET_REG(codec, SI3054_GPIO_CFG, 0x0); in si3054_init()
235 SET_REG(codec, SI3054_MISC_AFE, 0); in si3054_init()
236 SET_REG(code in si3054_init()
[all...]
/kernel/linux/linux-6.6/sound/pci/hda/
H A Dpatch_si3054.c65 #define SET_REG(codec,reg,val) (snd_hda_codec_write(codec,reg,0,SI3054_VERB_WRITE_NODE,val)) macro
143 SET_REG(codec, SI3054_LINE_RATE, substream->runtime->rate); in si3054_pcm_prepare()
147 SET_REG(codec, SI3054_LINE_LEVEL, val); in si3054_pcm_prepare()
217 SET_REG(codec, SI3054_LINE_RATE, 9600); in si3054_init()
218 SET_REG(codec, SI3054_LINE_LEVEL, SI3054_DTAG_MASK|SI3054_ATAG_MASK); in si3054_init()
219 SET_REG(codec, SI3054_EXTENDED_MID, 0); in si3054_init()
233 SET_REG(codec, SI3054_GPIO_POLARITY, 0xffff); in si3054_init()
234 SET_REG(codec, SI3054_GPIO_CFG, 0x0); in si3054_init()
235 SET_REG(codec, SI3054_MISC_AFE, 0); in si3054_init()
236 SET_REG(code in si3054_init()
[all...]
/kernel/linux/linux-5.10/drivers/clocksource/
H A Dasm9260_timer.c28 #define SET_REG 4 macro
115 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_set_next_event()
137 priv.base + HW_MCR + SET_REG); in asm9260_timer_set_oneshot()
151 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_set_periodic()
233 writel_relaxed(BM_C1_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_init()
/kernel/linux/linux-6.6/drivers/clocksource/
H A Dasm9260_timer.c28 #define SET_REG 4 macro
115 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_set_next_event()
137 priv.base + HW_MCR + SET_REG); in asm9260_timer_set_oneshot()
151 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_set_periodic()
233 writel_relaxed(BM_C1_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_init()
/kernel/linux/linux-5.10/drivers/irqchip/
H A Dirq-mxs.c29 #define SET_REG 4 macro
98 icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq)); in icoll_unmask_irq()
114 icoll_intr_reg(d) + SET_REG); in asm9260_unmask_irq()
H A Dalphascale_asm9260-icoll.h100 + SET_REG)
/kernel/linux/linux-6.6/drivers/irqchip/
H A Dirq-mxs.c29 #define SET_REG 4 macro
98 icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq)); in icoll_unmask_irq()
114 icoll_intr_reg(d) + SET_REG); in asm9260_unmask_irq()
H A Dalphascale_asm9260-icoll.h100 + SET_REG)
/kernel/linux/linux-5.10/arch/ia64/kernel/
H A Dhead.S1061 #define SET_REG(reg) \ define
1069 SET_REG(b1);
1070 SET_REG(b2);
1071 SET_REG(b3);
1072 SET_REG(b4);
1073 SET_REG(b5);
/kernel/linux/linux-6.6/arch/ia64/kernel/
H A Dhead.S1054 #define SET_REG(reg) \ define
1062 SET_REG(b1);
1063 SET_REG(b2);
1064 SET_REG(b3);
1065 SET_REG(b4);
1066 SET_REG(b5);
/kernel/linux/linux-5.10/drivers/media/dvb-frontends/
H A Dstv0910.c218 #define SET_REG(_reg, _val) \ macro
932 SET_REG(UPLCCST0, 0xe0); in init_search_param()
1687 SET_REG(DISTXFIFO, cmd->msg[i]); in send_master_cmd()
1709 SET_REG(DISTXFIFO, value); in send_burst()
/kernel/linux/linux-6.6/drivers/media/dvb-frontends/
H A Dstv0910.c209 #define SET_REG(_reg, _val) \ macro
923 SET_REG(UPLCCST0, 0xe0); in init_search_param()
1678 SET_REG(DISTXFIFO, cmd->msg[i]); in send_master_cmd()
1700 SET_REG(DISTXFIFO, value); in send_burst()
/kernel/linux/linux-6.6/drivers/tty/serial/
H A Dmxs-auart.c45 #define SET_REG 0x4 macro
500 writel_relaxed(val, addr + SET_REG); in mxs_set()
/kernel/linux/linux-5.10/drivers/tty/serial/
H A Dmxs-auart.c47 #define SET_REG 0x4 macro
510 writel_relaxed(val, addr + SET_REG); in mxs_set()

Completed in 15 milliseconds