Home
last modified time | relevance | path

Searched refs:RT (Results 1 - 25 of 29) sorted by relevance

12

/kernel/linux/linux-6.6/arch/mips/mm/
H A Duasm-mips.c51 [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
52 [insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD},
53 [insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD},
54 [insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
55 [insn_bbit0] = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
56 [insn_bbit1] = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
57 [insn_beq] = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
58 [insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
65 [insn_bne] = {M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
68 [insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIM
[all...]
H A Duasm-micromips.c43 [insn_addu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD},
44 [insn_addiu] = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
45 [insn_and] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD},
46 [insn_andi] = {M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
47 [insn_beq] = {M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
53 [insn_bne] = {M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM},
54 [insn_cache] = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM},
55 [insn_cfc1] = {M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS},
57 [insn_ctc1] = {M(mm_pool32f_op, 0, 0, 0, mm_ctc1_op, mm_32f_73_op), RT | RS},
62 [insn_divu] = {M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | R
[all...]
H A Duasm.c18 RT = 0x002, enumerator
/kernel/linux/linux-5.10/arch/mips/mm/
H A Duasm-mips.c51 [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
52 [insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD},
53 [insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD},
54 [insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
55 [insn_bbit0] = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
56 [insn_bbit1] = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
57 [insn_beq] = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
58 [insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
65 [insn_bne] = {M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
68 [insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIM
[all...]
H A Duasm-micromips.c43 [insn_addu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD},
44 [insn_addiu] = {M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
45 [insn_and] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD},
46 [insn_andi] = {M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM},
47 [insn_beq] = {M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
53 [insn_bne] = {M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM},
54 [insn_cache] = {M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM},
55 [insn_cfc1] = {M(mm_pool32f_op, 0, 0, 0, mm_cfc1_op, mm_32f_73_op), RT | RS},
57 [insn_ctc1] = {M(mm_pool32f_op, 0, 0, 0, mm_ctc1_op, mm_32f_73_op), RT | RS},
62 [insn_divu] = {M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | R
[all...]
H A Duasm.c18 RT = 0x002, enumerator
/kernel/linux/linux-5.10/arch/powerpc/crypto/
H A Dsha1-powerpc-asm.S26 #define RT(t) ((((t)+5)%6)+7) define
42 rotlwi RT(t),RA(t),5; \
45 add RT(t),RT(t),r6; \
49 add RT(t),RT(t),r14
54 rotlwi RT(t),RA(t),5; \
59 add RT(t),RT(t),r6; \
63 add RT(
[all...]
/kernel/linux/linux-6.6/arch/powerpc/crypto/
H A Dsha1-powerpc-asm.S26 #define RT(t) ((((t)+5)%6)+7) define
42 rotlwi RT(t),RA(t),5; \
45 add RT(t),RT(t),r6; \
49 add RT(t),RT(t),r14
54 rotlwi RT(t),RA(t),5; \
59 add RT(t),RT(t),r6; \
63 add RT(
[all...]
/kernel/linux/linux-5.10/arch/powerpc/xmon/
H A Dppc-opc.c520 equal the RT field. */
565 instruction or the RT field in a D, DS, X, XFX or XO form
568 #define RT RS
573 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
1726 equal the RT field. */
2322 /* The main opcode combined with an update code and the RT fields specified in
2687 /* An X_MASK with the RT field fixed. */
2705 /* An X_MASK with the RT and RA fields fixed. */
2708 /* An X_MASK with the RT and RB fields fixed. */
2714 /* An X_MASK with the RT, R
566 #define RT global() macro
[all...]
/kernel/linux/linux-6.6/arch/powerpc/xmon/
H A Dppc-opc.c520 equal the RT field. */
565 instruction or the RT field in a D, DS, X, XFX or XO form
568 #define RT RS
573 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
1726 equal the RT field. */
2322 /* The main opcode combined with an update code and the RT fields specified in
2687 /* An X_MASK with the RT field fixed. */
2705 /* An X_MASK with the RT and RA fields fixed. */
2708 /* An X_MASK with the RT and RB fields fixed. */
2714 /* An X_MASK with the RT, R
566 #define RT global() macro
[all...]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
H A Dst-pincfg.h20 #define RT (1 << 23) macro
51 #define SE_NICLK_IO (RT)
56 #define SE_ICLK_IO (RT | INVERTCLK)
61 #define DE_IO (RT | DOUBLE_EDGE)
66 #define ICLK (RT | CLKNOTDATA | INVERTCLK)
71 #define NICLK (RT | CLKNOTDATA)
/kernel/linux/linux-6.6/arch/arm/boot/dts/st/
H A Dst-pincfg.h20 #define RT (1 << 23) macro
51 #define SE_NICLK_IO (RT)
56 #define SE_ICLK_IO (RT | INVERTCLK)
61 #define DE_IO (RT | DOUBLE_EDGE)
66 #define ICLK (RT | CLKNOTDATA | INVERTCLK)
71 #define NICLK (RT | CLKNOTDATA)
/kernel/linux/linux-5.10/scripts/dtc/include-prefixes/arm/
H A Dst-pincfg.h20 #define RT (1 << 23) macro
51 #define SE_NICLK_IO (RT)
56 #define SE_ICLK_IO (RT | INVERTCLK)
61 #define DE_IO (RT | DOUBLE_EDGE)
66 #define ICLK (RT | CLKNOTDATA | INVERTCLK)
71 #define NICLK (RT | CLKNOTDATA)
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/arm/st/
H A Dst-pincfg.h20 #define RT (1 << 23) macro
51 #define SE_NICLK_IO (RT)
56 #define SE_ICLK_IO (RT | INVERTCLK)
61 #define DE_IO (RT | DOUBLE_EDGE)
66 #define ICLK (RT | CLKNOTDATA | INVERTCLK)
71 #define NICLK (RT | CLKNOTDATA)
/kernel/linux/linux-6.6/arch/x86/crypto/
H A Dtwofish-avx-x86_64-asm_64.S56 #define RT %xmm14 define
141 vpaddd x, RK1, RT;\
143 vpxor RT, c, c; \
146 vpsrld $1, c, RT; \
148 vpor c, RT, c; \
153 vpaddd x, RK1, RT;\
155 vpxor RT, c, c; \
/kernel/linux/linux-5.10/drivers/media/platform/rockchip/rga/
H A Drga-hw.c15 RT = 2, enumerator
92 LT, RT, LB, RB, in rga_lookup_draw_pos()
95 RT, LT, RB, LB, in rga_lookup_draw_pos()
98 RB, LB, RT, LT, in rga_lookup_draw_pos()
101 LB, RB, LT, RT, in rga_lookup_draw_pos()
113 case RT: in rga_lookup_draw_pos()
/kernel/linux/linux-6.6/drivers/media/platform/rockchip/rga/
H A Drga-hw.c15 RT = 2, enumerator
92 LT, RT, LB, RB, in rga_lookup_draw_pos()
95 RT, LT, RB, LB, in rga_lookup_draw_pos()
98 RB, LB, RT, LT, in rga_lookup_draw_pos()
101 LB, RB, LT, RT, in rga_lookup_draw_pos()
113 case RT: in rga_lookup_draw_pos()
/kernel/linux/linux-5.10/arch/x86/crypto/
H A Dtwofish-avx-x86_64-asm_64.S61 #define RT %xmm14 define
146 vpaddd x, RK1, RT;\
148 vpxor RT, c, c; \
151 vpsrld $1, c, RT; \
153 vpor c, RT, c; \
158 vpaddd x, RK1, RT;\
160 vpxor RT, c, c; \
/kernel/linux/linux-5.10/arch/nds32/mm/
H A Dalignment.c18 #define RT(inst) (((inst) >> 20) & 0x1FUL) macro
488 *idx_to_addr(regs, RT(inst)) = in do_32()
491 *idx_to_addr(regs, RT(inst)) = target_val; in do_32()
497 target_val = *idx_to_addr(regs, RT(inst)); in do_32()
/kernel/linux/linux-5.10/arch/arm/mach-sa1100/
H A Dsleep.S119 @ Step 1 clear RT field of all MSCx registers
/kernel/linux/linux-6.6/arch/arm/mach-sa1100/
H A Dsleep.S119 @ Step 1 clear RT field of all MSCx registers
/kernel/linux/linux-5.10/arch/mips/kernel/
H A Dtraps.c495 #define RT 0x001f0000 macro
553 regs->regs[(opcode & RT) >> 16] = value; in simulate_ll()
576 reg = (opcode & RT) >> 16; in simulate_sc()
665 int rt = (opcode & RT) >> 16; in simulate_rdhwr_normal()
709 #define CSR_FUNC_MASK RT
/kernel/linux/linux-6.6/arch/mips/kernel/
H A Dtraps.c504 #define RT 0x001f0000 macro
562 regs->regs[(opcode & RT) >> 16] = value; in simulate_ll()
585 reg = (opcode & RT) >> 16; in simulate_sc()
674 int rt = (opcode & RT) >> 16; in simulate_rdhwr_normal()
718 #define CSR_FUNC_MASK RT
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dsumod.h79 # define RT(x) ((x) << 0) macro
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dsumod.h79 # define RT(x) ((x) << 0) macro

Completed in 26 milliseconds

12