Lines Matching refs:RT
520 equal the RT field. */
565 instruction or the RT field in a D, DS, X, XFX or XO form
568 #define RT RS
573 /* The RS and RT fields of the DS form stq and DQ form lq instructions,
1726 equal the RT field. */
2322 /* The main opcode combined with an update code and the RT fields specified in
2687 /* An X_MASK with the RT field fixed. */
2705 /* An X_MASK with the RT and RA fields fixed. */
2708 /* An X_MASK with the RT and RB fields fixed. */
2714 /* An X_MASK with the RT, RA and RB fields fixed. */
2735 /* An X form instruction with RT fields specified */
2739 /* An X form instruction with RT and RA fields specified */
2792 /* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */
3106 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3107 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3113 {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3115 {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3147 {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3149 {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3152 {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3182 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3184 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3185 {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3186 {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3187 {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3188 {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3202 {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3203 {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3212 {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3213 {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3214 {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3215 {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3225 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3227 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3228 {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3229 {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3238 {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3239 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3240 {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3241 {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3242 {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3243 {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3253 {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3254 {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3261 {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3262 {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3263 {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3264 {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3298 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3321 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3332 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3334 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
3452 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3454 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3460 {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3462 {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3491 {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
3492 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
3493 {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3494 {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3495 {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
3496 {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
3506 {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3507 {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3516 {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3517 {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3518 {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3519 {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3540 {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3541 {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3571 {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3573 {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3576 {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3577 {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3600 {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3601 {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3624 {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3625 {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3626 {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3627 {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3653 {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3654 {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3677 {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3679 {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3682 {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3683 {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3709 {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3710 {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3730 {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3732 {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3735 {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3736 {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3738 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3739 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
3759 {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3766 {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3776 {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3792 {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3793 {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3794 {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3800 {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3803 {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3804 {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3805 {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3806 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3815 {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
3816 {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3817 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3824 {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3825 {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3826 {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
3827 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
3830 {"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3831 {"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3833 {"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3834 {"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3836 {"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}},
3848 {"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3849 {"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3850 {"subic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3852 {"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
3853 {"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}},
3854 {"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, NSI}},
3856 {"li", OP(14), DRA_MASK, PPCCOM, PPCVLE, {RT, SI}},
3857 {"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE, {RT, SI}},
3858 {"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}},
3859 {"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
3860 {"subi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSI}},
3861 {"la", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
3863 {"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE, {RT, SISIGNOPT}},
3864 {"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE, {RT, SISIGNOPT}},
3865 {"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3866 {"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}},
3867 {"subis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, NSISIGNOPT}},
4154 {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
4155 {"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
4704 {"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4705 {"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4706 {"subc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4707 {"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4708 {"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4709 {"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
4711 {"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4712 {"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4714 {"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4715 {"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4716 {"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4717 {"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4719 {"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4720 {"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4724 {"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4731 {"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}},
4732 {"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}},
4734 {"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}},
4736 {"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}},
4740 {"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
4741 {"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4762 {"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4767 {"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4780 {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4784 {"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}},
4788 {"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}},
4790 {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}},
4792 {"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4793 {"sub", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RB, RA}},
4794 {"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4795 {"sub.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RB, RA}},
4802 {"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
4804 {"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}},
4808 {"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}},
4809 {"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}},
4841 {"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
4842 {"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
4844 {"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
4845 {"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
4852 {"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}},
4854 {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
4859 {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
4861 {"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
4868 {"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}},
4869 {"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}},
4871 {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
4872 {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
4882 {"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}},
4886 {"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}},
4897 {"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
4906 {"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4907 {"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4908 {"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4909 {"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4911 {"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4912 {"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4913 {"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
4914 {"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
4929 {"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4930 {"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
4958 {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
4968 {"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}},
4990 {"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
4991 {"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
4992 {"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
4993 {"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
4995 {"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
4996 {"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
4997 {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
4998 {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5009 {"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}},
5030 {"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5031 {"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5032 {"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5033 {"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5035 {"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5036 {"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5038 {"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5039 {"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5040 {"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5041 {"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5043 {"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5044 {"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5045 {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5046 {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5069 {"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5081 {"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5082 {"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5084 {"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}},
5086 {"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5087 {"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5088 {"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5089 {"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5091 {"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}},
5101 {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
5105 {"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}},
5106 {"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}},
5113 {"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}},
5120 {"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5129 {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
5138 {"ldmx", X(31,309), X_MASK, POWER9, 0, {RT, RA0, RB}},
5140 {"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5142 {"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}},
5149 {"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}},
5151 {"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}},
5152 {"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}},
5153 {"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}},
5154 {"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}},
5155 {"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}},
5156 {"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}},
5157 {"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}},
5158 {"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}},
5159 {"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}},
5160 {"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}},
5161 {"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}},
5162 {"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}},
5163 {"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}},
5164 {"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}},
5165 {"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}},
5166 {"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}},
5167 {"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}},
5168 {"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}},
5169 {"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}},
5170 {"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}},
5171 {"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}},
5172 {"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}},
5173 {"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}},
5174 {"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}},
5175 {"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}},
5176 {"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}},
5177 {"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}},
5178 {"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}},
5179 {"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}},
5180 {"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}},
5181 {"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}},
5182 {"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}},
5183 {"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}},
5184 {"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}},
5185 {"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}},
5186 {"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}},
5190 {"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}},
5192 {"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5193 {"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5197 {"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}},
5198 {"mftmr", X(31,366), X_MASK, PPCTMR|E6500, 0, {RT, TMR}},
5202 {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}},
5203 {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}},
5204 {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}},
5205 {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}},
5206 {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}},
5207 {"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}},
5208 {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}},
5209 {"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}},
5210 {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}},
5211 {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}},
5212 {"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN, {RT}},
5213 {"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1, {RT}},
5214 {"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, 0, {RT}},
5215 {"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN, {RT}},
5216 {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}},
5217 {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}},
5218 {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}},
5219 {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}},
5220 {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}},
5221 {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}},
5222 {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}},
5223 {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}},
5224 {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}},
5225 {"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, 0, {RT}},
5226 {"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, 0, {RT}},
5227 {"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, 0, {RT}},
5228 {"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, 0, {RT}},
5229 {"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, 0, {RT}},
5230 {"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, 0, {RT}},
5231 {"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, 0, {RT}},
5232 {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}},
5233 {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}},
5234 {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}},
5235 {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}},
5236 {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}},
5237 {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}},
5238 {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}},
5239 {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}},
5240 {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}},
5241 {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}},
5242 {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}},
5243 {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}},
5244 {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}},
5245 {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5246 {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5247 {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5248 {"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, 0, {RT}},
5249 {"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5250 {"mftb", X(31,339), X_MASK, POWER4|BOOKE, 0, {RT, TBR}},
5251 {"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, 0, {RT}},
5252 {"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, 0, {RT}},
5253 {"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, 0, {RT}},
5254 {"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, 0, {RT}},
5255 {"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, 0, {RT}},
5256 {"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, 0, {RT}},
5257 {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}},
5258 {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}},
5259 {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}},
5260 {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}},
5261 {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}},
5262 {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}},
5263 {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}},
5264 {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}},
5265 {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}},
5266 {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}},
5267 {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}},
5268 {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}},
5269 {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}},
5270 {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}},
5271 {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}},
5272 {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}},
5273 {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}},
5274 {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}},
5275 {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}},
5276 {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}},
5277 {"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, 0, {RT}},
5278 {"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, 0, {RT}},
5279 {"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, 0, {RT}},
5280 {"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, 0, {RT}},
5281 {"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, 0, {RT}},
5282 {"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, 0, {RT}},
5283 {"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, 0, {RT}},
5284 {"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, 0, {RT}},
5285 {"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, 0, {RT}},
5286 {"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, 0, {RT}},
5287 {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}},
5288 {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}},
5289 {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
5290 {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}},
5291 {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}},
5292 {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}},
5293 {"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, 0, {RT}},
5294 {"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5295 {"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, 0, {RT}},
5296 {"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5297 {"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, 0, {RT}},
5298 {"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, 0, {RT}},
5299 {"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5300 {"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN, {RT, SPRBAT}},
5301 {"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, 0, {RT}},
5302 {"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, 0, {RT}},
5303 {"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, 0, {RT}},
5304 {"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, 0, {RT}},
5305 {"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, 0, {RT}},
5306 {"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, 0, {RT}},
5307 {"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, 0, {RT}},
5308 {"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, 0, {RT}},
5309 {"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, 0, {RT}},
5310 {"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN, {RT}},
5311 {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}},
5312 {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}},
5313 {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}},
5314 {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}},
5315 {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}},
5316 {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}},
5317 {"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, 0, {RT}},
5318 {"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, 0, {RT}},
5319 {"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, 0, {RT}},
5320 {"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, 0, {RT}},
5321 {"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, 0, {RT}},
5322 {"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, 0, {RT}},
5323 {"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, 0, {RT}},
5324 {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}},
5325 {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}},
5326 {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}},
5327 {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}},
5328 {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}},
5329 {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}},
5330 {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}},
5331 {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}},
5332 {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}},
5333 {"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}},
5334 {"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}},
5335 {"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}},
5336 {"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, 0, {RT}},
5337 {"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, 0, {RT}},
5338 {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}},
5339 {"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}},
5340 {"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}},
5341 {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}},
5342 {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}},
5343 {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}},
5344 {"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, 0, {RT}},
5345 {"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, 0, {RT}},
5346 {"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, 0, {RT}},
5347 {"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, 0, {RT}},
5348 {"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, 0, {RT}},
5349 {"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, 0, {RT}},
5350 {"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, 0, {RT}},
5351 {"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, 0, {RT}},
5352 {"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, 0, {RT}},
5353 {"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, 0, {RT}},
5354 {"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, 0, {RT}},
5355 {"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, 0, {RT}},
5356 {"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, 0, {RT}},
5357 {"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, 0, {RT}},
5358 {"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, 0, {RT}},
5359 {"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, 0, {RT}},
5360 {"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, 0, {RT}},
5361 {"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, 0, {RT}},
5362 {"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, 0, {RT}},
5363 {"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, 0, {RT}},
5364 {"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, 0, {RT}},
5365 {"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, 0, {RT}},
5366 {"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, 0, {RT}},
5367 {"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, 0, {RT}},
5368 {"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, 0, {RT}},
5369 {"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, 0, {RT}},
5370 {"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, 0, {RT}},
5371 {"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, 0, {RT}},
5372 {"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, 0, {RT}},
5373 {"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, 0, {RT}},
5374 {"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, 0, {RT}},
5375 {"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, 0, {RT}},
5376 {"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, 0, {RT}},
5377 {"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, 0, {RT}},
5378 {"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, 0, {RT}},
5379 {"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, 0, {RT}},
5380 {"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, 0, {RT}},
5381 {"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, 0, {RT}},
5382 {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}},
5383 {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}},
5384 {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}},
5385 {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}},
5387 {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}},
5388 {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}},
5389 {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}},
5390 {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}},
5391 {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}},
5392 {"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, 0, {RT}},
5393 {"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, 0, {RT}},
5394 {"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, 0, {RT}},
5395 {"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, 0, {RT}},
5396 {"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, 0, {RT}},
5397 {"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, 0, {RT}},
5398 {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
5399 {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
5400 {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
5401 {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
5402 {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
5404 {"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}},
5408 {"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}},
5412 {"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}},
5413 {"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}},
5415 {"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}},
5416 {"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}},
5422 {"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4, {RT}},
5423 {"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}},
5424 {"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4, {RT}},
5426 {"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}},
5430 {"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}},
5442 {"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5443 {"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5444 {"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5445 {"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5474 {"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5475 {"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5476 {"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5477 {"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
5487 {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
5547 {"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5548 {"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5550 {"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5551 {"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5731 {"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2|PPC476, {RT, RA0, RB}},
5737 {"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}},
5738 {"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}},
5740 {"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5741 {"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5743 {"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5744 {"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5751 {"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}},
5759 {"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
5760 {"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
5767 {"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5768 {"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5769 {"subco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5770 {"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5771 {"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5772 {"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RB, RA}},
5774 {"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5775 {"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5776 {"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5777 {"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5781 {"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}},
5783 {"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}},
5785 {"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}},
5786 {"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5788 {"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}},
5789 {"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}},
5810 {"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
5811 {"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
5820 {"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
5821 {"subo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RB, RA}},
5822 {"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
5823 {"subo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RB, RA}},
5834 {"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
5835 {"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
5839 {"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}},
5845 {"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}},
5847 {"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}},
5848 {"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}},
5865 {"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}},
5869 {"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}},
5873 {"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}},
5874 {"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}},
5876 {"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
5877 {"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
5879 {"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}},
5895 {"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5896 {"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5897 {"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5898 {"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5900 {"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5901 {"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5902 {"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
5903 {"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
5905 {"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}},
5954 {"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5955 {"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5956 {"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5957 {"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5959 {"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5960 {"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5961 {"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5962 {"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5977 {"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}},
5988 {"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5989 {"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5990 {"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5991 {"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
5993 {"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
5994 {"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
5996 {"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}},
5997 {"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}},
5998 {"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}},
5999 {"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}},
6001 {"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6002 {"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6003 {"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6004 {"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6010 {"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}},
6028 {"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6029 {"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6031 {"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6032 {"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6033 {"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}},
6034 {"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}},
6036 {"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}},
6037 {"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}},
6046 {"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}},
6048 {"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}},
6072 {"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}},
6076 {"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}},
6094 {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6095 {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6105 {"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6106 {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
6108 {"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}},
6119 {"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}},
6120 {"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}},
6122 {"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
6123 {"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
6131 {"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}},
6145 {"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6146 {"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6147 {"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6148 {"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6158 {"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
6159 {"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}},
6189 {"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6190 {"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6191 {"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6192 {"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}},
6199 {"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6200 {"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2, {RT, RA}},
6221 {"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6222 {"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6224 {"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6225 {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6231 {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, 0, {RT, RA}},
6232 {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, 0, {RT, RA}},
6235 {"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}},
6252 {"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}},
6253 {"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}},
6255 {"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}},
6256 {"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}},
6258 {"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}},
6259 {"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}},
6289 {"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}},
6290 {"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
6292 {"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}},
6293 {"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
6295 {"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
6297 {"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
6309 {"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
6311 {"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
6313 {"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}},
6315 {"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}},
6321 {"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}},
6322 {"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}},
6353 {"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
6354 {"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}},
6355 {"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
6605 {"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
6606 {"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}},
7022 {"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7023 {"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7024 {"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7025 {"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7026 {"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7027 {"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7028 {"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
7029 {"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7030 {"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7031 {"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
7039 {"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7040 {"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7041 {"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7042 {"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7043 {"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7044 {"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7045 {"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7046 {"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7047 {"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
7058 {"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
7059 {"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7060 {"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
7070 {"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7071 {"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7072 {"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7084 {"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7085 {"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7086 {"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7087 {"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
7111 {"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}},
7113 {"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RT, SH, MBE, ME}},