162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci#ifndef _ST_PINCFG_H_ 362306a36Sopenharmony_ci#define _ST_PINCFG_H_ 462306a36Sopenharmony_ci 562306a36Sopenharmony_ci/* Alternate functions */ 662306a36Sopenharmony_ci#define ALT1 1 762306a36Sopenharmony_ci#define ALT2 2 862306a36Sopenharmony_ci#define ALT3 3 962306a36Sopenharmony_ci#define ALT4 4 1062306a36Sopenharmony_ci#define ALT5 5 1162306a36Sopenharmony_ci#define ALT6 6 1262306a36Sopenharmony_ci#define ALT7 7 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_ci/* Output enable */ 1562306a36Sopenharmony_ci#define OE (1 << 27) 1662306a36Sopenharmony_ci/* Pull Up */ 1762306a36Sopenharmony_ci#define PU (1 << 26) 1862306a36Sopenharmony_ci/* Open Drain */ 1962306a36Sopenharmony_ci#define OD (1 << 25) 2062306a36Sopenharmony_ci#define RT (1 << 23) 2162306a36Sopenharmony_ci#define INVERTCLK (1 << 22) 2262306a36Sopenharmony_ci#define CLKNOTDATA (1 << 21) 2362306a36Sopenharmony_ci#define DOUBLE_EDGE (1 << 20) 2462306a36Sopenharmony_ci#define CLK_A (0 << 18) 2562306a36Sopenharmony_ci#define CLK_B (1 << 18) 2662306a36Sopenharmony_ci#define CLK_C (2 << 18) 2762306a36Sopenharmony_ci#define CLK_D (3 << 18) 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci/* User-frendly defines for Pin Direction */ 3062306a36Sopenharmony_ci /* oe = 0, pu = 0, od = 0 */ 3162306a36Sopenharmony_ci#define IN (0) 3262306a36Sopenharmony_ci /* oe = 0, pu = 1, od = 0 */ 3362306a36Sopenharmony_ci#define IN_PU (PU) 3462306a36Sopenharmony_ci /* oe = 1, pu = 0, od = 0 */ 3562306a36Sopenharmony_ci#define OUT (OE) 3662306a36Sopenharmony_ci /* oe = 1, pu = 0, od = 1 */ 3762306a36Sopenharmony_ci#define BIDIR (OE | OD) 3862306a36Sopenharmony_ci /* oe = 1, pu = 1, od = 1 */ 3962306a36Sopenharmony_ci#define BIDIR_PU (OE | PU | OD) 4062306a36Sopenharmony_ci 4162306a36Sopenharmony_ci/* RETIME_TYPE */ 4262306a36Sopenharmony_ci/* 4362306a36Sopenharmony_ci * B Mode 4462306a36Sopenharmony_ci * Bypass retime with optional delay parameter 4562306a36Sopenharmony_ci */ 4662306a36Sopenharmony_ci#define BYPASS (0) 4762306a36Sopenharmony_ci/* 4862306a36Sopenharmony_ci * R0, R1, R0D, R1D modes 4962306a36Sopenharmony_ci * single-edge data non inverted clock, retime data with clk 5062306a36Sopenharmony_ci */ 5162306a36Sopenharmony_ci#define SE_NICLK_IO (RT) 5262306a36Sopenharmony_ci/* 5362306a36Sopenharmony_ci * RIV0, RIV1, RIV0D, RIV1D modes 5462306a36Sopenharmony_ci * single-edge data inverted clock, retime data with clk 5562306a36Sopenharmony_ci */ 5662306a36Sopenharmony_ci#define SE_ICLK_IO (RT | INVERTCLK) 5762306a36Sopenharmony_ci/* 5862306a36Sopenharmony_ci * R0E, R1E, R0ED, R1ED modes 5962306a36Sopenharmony_ci * double-edge data, retime data with clk 6062306a36Sopenharmony_ci */ 6162306a36Sopenharmony_ci#define DE_IO (RT | DOUBLE_EDGE) 6262306a36Sopenharmony_ci/* 6362306a36Sopenharmony_ci * CIV0, CIV1 modes with inverted clock 6462306a36Sopenharmony_ci * Retiming the clk pins will park clock & reduce the noise within the core. 6562306a36Sopenharmony_ci */ 6662306a36Sopenharmony_ci#define ICLK (RT | CLKNOTDATA | INVERTCLK) 6762306a36Sopenharmony_ci/* 6862306a36Sopenharmony_ci * CLK0, CLK1 modes with non-inverted clock 6962306a36Sopenharmony_ci * Retiming the clk pins will park clock & reduce the noise within the core. 7062306a36Sopenharmony_ci */ 7162306a36Sopenharmony_ci#define NICLK (RT | CLKNOTDATA) 7262306a36Sopenharmony_ci#endif /* _ST_PINCFG_H_ */ 73